[VHDL/FPGA/Verilog] Tetris
在SystemVerilog中创建的俄罗斯方块
Tetris created in SystemVerilog (2023-12-30, Others, 0KB, 下载0次)
[VHDL/FPGA/Verilog] verilog-ManchesterCoding
verilog实现的曼彻斯特和差分曼彻斯特编码。压缩包中有源码和结果截图，代码又注释。
The implementation of Manchester Coding and differential Manchester Coding. The file has the source code and the picture of the result. The code is explanatory. (2017-01-10, Others, 93KB, 下载45次)
[VHDL/FPGA/Verilog] 4.2
曼切斯特编码，解码Verilog源代码
nrz,1553协议通信采用的编解码方式
Manchester encoding, decoding, Verilog source code (2014-09-29, Others, 97KB, 下载38次)
[VHDL/FPGA/Verilog] half_sub
用Verilog语言实现的半加器功能，非常好的例程。
Verilog language implementation with half adder function, very good routine. (2014-07-31, Others, 228KB, 下载1次)
[VHDL/FPGA/Verilog] iirbandpass
基于matlab的iir巴特沃斯的带通滤波器设计，非常好用
Based on the matlab iir Butterworth bandpass filter design, very easy to use (2013-08-23, Others, 1KB, 下载8次)
[VHDL/FPGA/Verilog] iic_com
iic代码verilog，如果有什么特别的问题，请加593283938，详细交流
iic verilog (2013-08-02, Others, 2KB, 下载3次)
[VHDL/FPGA/Verilog] fsmd_examples
fsm有限状态机加datapath的一个例子
fsm finite state machine plus datapath example (2013-03-12, Others, 6KB, 下载6次)
[VHDL/FPGA/Verilog] butterworth-filter
巴特沃斯滤波器的ppt，里面详细的介绍的巴特沃斯滤波器的原理及其设计方法，对于滤波器的使用提供很好的学习作用
Butterworth filter ppt, which detailed Butterworth filter described principle and design method for the use of the filter to provide a good learning (2013-03-04, Others, 419KB, 下载6次)
[VHDL/FPGA/Verilog] plus
在ise环境下，用vorilog hdl语言实现全加器算法
To achieve full adders algorithm ise environment, vorilog hdl language (2012-12-01, Others, 16KB, 下载3次)
[VHDL/FPGA/Verilog] shumaxiangkuang
数码相框，tft彩屏加SDHC，读取SDHC卡里面的图片在TFT彩屏上显示
sdhc program (2012-03-20, Others, 85KB, 下载8次)
[VHDL/FPGA/Verilog] nRF24le1
nRF24le，功能為無線傳輸加類比取樣
nRF24le, plus analog wireless transmission function for the sampling (2012-02-01, Others, 145KB, 下载21次)
[VHDL/FPGA/Verilog] Adder4
源码，内容是用VHDL语言编写的四位全加器
Source code, using VHDL language of the four full-adder (2010-01-19, Others, 5KB, 下载2次)
[VHDL/FPGA/Verilog] f_adder
在EDA的MAX+PLUS II开发环境下用VHDL编写的全加器
In the EDA (2008-05-07, Others, 55KB, 下载3次)
[VHDL/FPGA/Verilog] reg_add
在quartus中仿真通过的移位加程序的vhdl代码
In the Quartus simulation procedures adopted by the transposition of the VHDL code (2008-01-08, Others, 511KB, 下载5次)
[VHDL/FPGA/Verilog] DCT_1D
一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper
One-dimensional DCT transform Verilog source code can be used to optimize the JPEG algorithm reference. Procedures used in the algorithm known as the (2007-10-25, Others, 53KB, 下载71次)
[VHDL/FPGA/Verilog] 10vhdlexamples
10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。
10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on. (2007-07-30, Others, 41KB, 下载55次)
[VHDL/FPGA/Verilog] cpldcodec
用CPLD控制曼彻斯特编解码器，很详细的文字说明。
with CPLD control of Manchester codecs, very detailed notes. (2007-01-15, Others, 119KB, 下载83次)
[VHDL/FPGA/Verilog] FPGAMILSTD1553B
介绍用FPGA设计实现MIL-STD1553B部接口中的曼彻斯特码编解码器
presentation FPGA Design MIL-STD1553B Ministry interface Manchester encoding and decoding (2007-01-15, Others, 94KB, 下载68次)
[VHDL/FPGA/Verilog] half_add
一个用VHDL语言编写的全加器，是数字电路EDA设计的一个例子，可能不太特别，但是应该可以用一下的。
a VHDL prepared by the full adder, digital circuit design of an EDA example, may not be special, but should be able to use what they are doing. (2006-11-28, Others, 16KB, 下载156次)
[VHDL/FPGA/Verilog] jiafaqi
实现四位加法器的VHDL代码，里面含有全加器的代码
achieve four Adder VHDL code, which contains the full adder code (2006-10-25, Others, 1KB, 下载2次)