基于FPGA的莫尔斯码解码器
FPGA based Morse Code decoder (2024-04-18, Verilog, 0KB, 下载0次)
俄罗斯方块游戏的FPGA Verilog实现
Verilog implementation of Tetris game for FPGA (2024-02-08, Verilog, 0KB, 下载0次)
莫尔斯代码Verilog
Mores Code Verilog (2024-01-10, Verilog, 0KB, 下载0次)
使用伊维里洛制作并使用Vivado合成的加法器，
Adders made using iverilog and synthesised using Vivado, (2018-10-31, Verilog, 0KB, 下载0次)
卡米尼奥·德·达多斯（Caminho de dados feito em verilog），
Caminho de dados feito em verilog, (2023-07-20, Verilog, 0KB, 下载0次)
基于Box-Mueller方法的FPGA加性高斯白噪声发生器
FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method (2016-10-07, Verilog, 4537KB, 下载0次)
基于FPGA的俄罗斯方块游戏
tetris game on FPGA (2016-06-05, Verilog, 14KB, 下载0次)
用于俄罗斯方块游戏的FPGA实现。
a FPGA implementation for tetris game. (2016-06-18, Verilog, 2156KB, 下载0次)
带ULX3S的FPGA奥德修斯
FPGA Odysseus with ULX3S (2019-06-04, Verilog, 5114KB, 下载0次)
二进制单精度浮点融合乘加单元设计（Verilog HDL）
Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL) (2013-07-08, Verilog, 4059KB, 下载0次)
Verilog俄罗斯方块
Verilog Tetris (2014-12-25, Verilog, 7KB, 下载1次)
流行视频游戏俄罗斯方块的Verilog实现。
A Verilog implementation of the popular video game Tetris. (2015-10-28, Verilog, 14KB, 下载0次)
FPGA实现中的又一个俄罗斯方块
Yet Another Tetris on FPGA Implementation (2021-05-27, Verilog, 101KB, 下载0次)
使用Verilog语言编程实现用有限状态机实现序列检测、全加器、AD转换等功能
Sequence detection with finite state machine (2020-01-14, Verilog, 2KB, 下载1次)
32位全加器设计，插入流水线，实现各数据同步
Design of 32-bit full adder, insert pipeline to realize data synchronization (2019-05-19, Verilog, 4KB, 下载1次)
使用DE2开发板的VGA模块，来仿真实现一维元胞自动机。
The VGA module of DE2 development board is used to simulate and realize one-dimensional cellular automata. (2019-04-21, Verilog, 1645KB, 下载0次)
华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度
The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed (2018-09-15, Verilog, 4KB, 下载25次)
本设计是verilog设计的俄罗斯方块，含有所有的源代码。
This design is Verilog designed Tetris, which contains all the source code. (2018-07-30, Verilog, 8618KB, 下载1次)
移位寄存器模块用于存储串行输入滤波器的数据；乘加计算模块用于fir计算
The shift register module is used to store data of serial input filter, and the multiplier calculation module is used for FIR calculation. (2018-06-30, Verilog, 1KB, 下载3次)
布斯(Booth)乘法器是一種透過編碼後再運算所得到較佳效能乘法器
請嘗試描述說明
1. 布斯乘法器原理
2. 布斯乘法器組成架構
3. 並嘗試完成布斯乘法器
The Booth multiplier is a better performance multiplier that is encoded and then computed
Please try to describe the description
1. Booth multiplier principle
Booth multiplier structure
3. And try to complete the Booth multiplier (2018-01-07, Verilog, 67KB, 下载3次)