[VHDL/FPGA/Verilog] FPGA-HDL-MORSE-CODE-ENCODER
FPGA HDL莫尔斯码编码器
FPGA HDL MORSE CODE ENCODER (2024-05-11, Others, 0KB, 下载0次)
[VHDL/FPGA/Verilog] vhdl-is-still-cool
有趣的vhdl内容与我的朋友克里斯蒂安
fun vhdl stuff w my friend cristian (2024-03-02, Others, 0KB, 下载0次)
[VHDL/FPGA/Verilog] 4位全加器 计数器等程序
EDA仿真工具使用的，进行EDA开发的多个程序；
包括：4位全加器，12分频，128分频，篮球计数秒表（部分），计数器；
可以搭配EDA仿真软件使用，也可以搭配开发板使用；
EDA simulation tools used for EDA development of multiple programs;
Including: 4 bit full adder, 12 frequency division, 128 frequency division, basketball counting stopwatch (part), counter;
It can be used with EDA simulation software or with development board. (2018-04-21, Others, 1KB, 下载1次)
[VHDL/FPGA/Verilog] alu
用Verilog语言中的always块实现对输入数据执行加、减、与、或和求反的功能
Using Verilog language always realize the input data block to perform addition, subtraction, AND, OR, and negated function (2016-05-16, Others, 1KB, 下载1次)
[VHDL/FPGA/Verilog] tanchishe
VHDL实现的贪吃蛇，碰到自己身体或规定范围壁障游戏结束，每吃3个点身体长度加1
VHDL Snake (2016-01-05, Others, 3KB, 下载2次)
[VHDL/FPGA/Verilog] batewosi
低通和高通分别作卷积的方法。用巴特沃斯滤波器构造数字二分频器。
Low-pass and high-pass respectively, for convolution approach. Digital Butterworth filter structure with two dividers. (2013-06-27, Others, 1KB, 下载5次)
[VHDL/FPGA/Verilog] Russiafont
开发手机，led显示屏等经常需要俄罗斯字体库，这个是标准俄罗斯字体库，ttf格式的。
The development of mobile phones, led display often need the the Russian font library, this is the standard Russian font library, ttf format. (2012-12-17, Others, 17KB, 下载6次)
[VHDL/FPGA/Verilog] mips_single
這是以verilog所撰寫的MIPS single CPU文件檔。可完成簡單的加減運算。
This is the verilog are written in MIPS single CPU document file. To be completed by the simple addition and subtraction. (2012-07-19, Others, 5KB, 下载5次)
[VHDL/FPGA/Verilog] coder-decoder
基于FPGA的8路并行数据加2路视频数据的编解码
FPGA-based 8-way parallel data plus 2 video encoding and decoding of data (2011-11-09, Others, 1722KB, 下载6次)
[VHDL/FPGA/Verilog] Vr74x163
用Verilog HDL语言写一个计数器，每当时钟到来时计数器加1.
Verilog HDL language used to write a counter, when the clock arrives counter plus 1. (2011-03-07, Others, 269KB, 下载6次)
[VHDL/FPGA/Verilog] standard_sim_tb
xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪
the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise (2009-09-22, Others, 13KB, 下载12次)
[VHDL/FPGA/Verilog] out
verilog语言编写的米勒解码的输出模块加仿真波形正确了
Miller verilog language decoder output waveform simulation module plus correct (2009-06-19, Others, 229KB, 下载29次)
[VHDL/FPGA/Verilog] full_adder3
三位全加器的源代码，和测试代码，用Verilog HDL实现的！
The three full adder of the source code, and test code, using Verilog HDL to achieve! (2008-03-18, Others, 35KB, 下载11次)
[VHDL/FPGA/Verilog] add_ff8cin
触发器实现的，8位全加器的VHDL语言实现，适用于altera系列的FPGA
Flip-flop to achieve, eight full adder realize the VHDL language, applicable to altera series FPGA (2007-11-01, Others, 1KB, 下载13次)
[VHDL/FPGA/Verilog] add_ff8
利用触发器实现的，8位半加器的VHDL语言实现，适用于altera系列FPGA
Realize the use of triggers, and 8-bit half adder of the VHDL language, applicable to altera Series FPGA (2007-11-01, Others, 1KB, 下载2次)
[VHDL/FPGA/Verilog] h_adder
本文件包是在MAX+plus II 软件环境下实现全加器的逻辑功能
This document packet was MAX+ Plus II software environment to achieve full adder logic function (2007-10-05, Others, 13KB, 下载1次)
[VHDL/FPGA/Verilog] eluosi_game
这是一个基于NIOSII的俄罗斯方块游戏设计，是基于FPGA的，利用流模式DMA传输实现游戏。
This is a box based on the Russian NIOSII game design, is based on the FPGA, and the use of streaming mode DMA transfer realize the game. (2007-09-29, Others, 8351KB, 下载139次)
[VHDL/FPGA/Verilog] S6_VGA_change
verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，
Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off, (2007-09-09, Others, 2512KB, 下载177次)
[VHDL/FPGA/Verilog] CMI
用ＭＡＸＰＬＵＳ设计的ＣＭＩ程序，好不容易弄到的，
MAXPLUS designed by CMI procedures, easy to get, and (2007-08-31, Others, 31KB, 下载32次)
[VHDL/FPGA/Verilog] 399
用VHDL编写的8位全加器,数字分频器等程序
VHDL prepared by the eight All-Canadian, digital dividers procedures (2006-05-20, Others, 556KB, 下载26次)