在Intel FPGA lite 18.0上使用Verilog HDL的莫尔斯码生成器
Morse code generator using Verilog HDL on Intel FPGA lite 18.0 (2024-03-17, Verilog, 0KB, 下载0次)
Xilinx Zynq系列开发板ZedBoard,vga显示，实现基本功能
Xilinx Zynq series development board ZedBoard, vga display, implementing basic functions (2024-03-06, Verilog, 5441KB, 下载0次)
Desarrollo de ejercicios varios en Verilog para la pela FPGA锡林克斯Basys 3。FPGA部件#XC7A35T-1CPG236C，
Desarrollo de ejercicios varios en Verilog para la placa FPGA Basys 3 de Xilinx. FPGA Part # XC7A35T-1CPG236C, (2023-09-08, Verilog, 0KB, 下载0次)
纳斯达克HFT FPGA项目低延迟以太网模块的RTL实现。，
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project., (2023-08-12, Verilog, 0KB, 下载0次)
伊斯兰阿扎德大学数字系统VHDL练习
VHDL Exercises for Digital Systems at Qazvin islamic azad university (2023-01-15, Verilog, 912KB, 下载0次)
用Verilog编写的FPGA俄罗斯方块
FPGA Tetris written in Verilog (2018-04-26, Verilog, 121KB, 下载0次)
Verilog中的俄罗斯方块——浙江大学逻辑与计算机设计基础课程的一个课程项目。
Tetris in Verilog -- a course project for Logic and Computer Design Fundamentals Course at ZJU. (2021-12-19, Verilog, 14095KB, 下载1次)
SPI从接口的Verilog实现。针对Atlys devkit（赛灵思斯巴达-6）控制的...
Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter (2012-04-13, Verilog, 3258KB, 下载0次)
斯坦福数字IC课件，有关IC的设计与优化，对Verilog编程更加得心应手
Stanford Digital IC courseware, about IC design and optimization, is more handy for Verilog programming (2021-01-22, Verilog, 7287KB, 下载1次)
单周期的布斯乘法器，已经通过quartusii 13功能验证。booth乘法器
a booth multiplexer by one cycle, which is qualified in quartus ii (2021-01-19, Verilog, 1KB, 下载0次)
ADC8694四同道轮循读取，超高的的采样频率，硬件就没加保持器
Adc8694 is read in four cycles with ultra-high sampling frequency. The hardware does not add a holder (2020-10-08, Verilog, 12805KB, 下载0次)
实现一位加法器，用于basys3开发板，将管教重新分配，可以适用于所有的开发板
one bit full adder, designed for basys3 board, you can change the footprint nember to suit other board! (2019-04-27, Verilog, 398KB, 下载0次)
并行传输啊实打烤面筋啊算了带回家开塞露萨达阿斯顿撒萨达
AD7606 /Verilg/ Parallel transmission (2019-04-16, Verilog, 2KB, 下载1次)
AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明
AD7760 Full Function Support with Additional Instructions (2018-12-21, Verilog, 35202KB, 下载42次)
16位无符号浮点数与定点数的加法器与乘法器
16-bit floating-point and fixed-point adder and multiplier in Verilog (2018-12-16, Verilog, 2KB, 下载6次)
verilog实现3-8译码器改全加器，硬件为小脚丫MAX10M02SCM153
Verilog implements 3-8 decoder to full adder. The hardware is small foot MAX10M02SCM153. (2018-11-29, Verilog, 4439KB, 下载0次)
图像边缘加测
sobel算法实现
FPGA
可进行并行处理
Image edge measurement (2018-08-16, Verilog, 21725KB, 下载13次)
实现可调维度的浮点数加法运算，内涵各个子模块和testbench
Able to achieve the float numbers adding operation. (2017-12-26, Verilog, 81KB, 下载10次)
有关于M序列的曼彻斯特编码，亲自验证有效。
The Manchester code of the M sequence is personally validated. (2017-08-05, Verilog, 3026KB, 下载3次)
全加器LED点亮的原理是，根据LED硬件电路接法给相应的端口高电平或者低电平即可点亮。
LED light principle is, according to the LED hardware circuit connection to the corresponding port, high or low level can light. (2017-07-08, Verilog, 362KB, 下载1次)