是国外的成品模型，实现用SDRAM运行nios，同时用SRAM保存摄像头数据，计算一维光子晶体的透射特性和反射特性。
Foreign model is finished, Implemented with SDRAM run nios, while saving camera data SRAM, Calculated transmission characteristics and reflection characteristics of the one-dimensional photonic crystals. (2017-04-27, Others, 8KB, 下载2次)
一个简单的ALU程序设计，实现以下功能：
逻辑运算：与、或、非、异或、逻辑左移、逻辑右移
算术运算：加、减
A simple ALU program designed to achieve the following functions: logic operations: AND, OR, NOT, XOR logical left, logical shift right arithmetic operations: addition, subtraction (2016-05-03, Others, 580KB, 下载1次)
在Xillinx ISE 平台上利用VHDL语言实现同步计数器，利用状态机实现，导入FPGA版点亮7段数码管并实现加、减计数功能。
The programme realizes a counter based on synchronous state machines, and it can be download to a FPGA chip. (2015-06-16, Others, 1464KB, 下载1次)
ad9708与ad9280的程序，ad采集进来再da输出，在中间可以自行加一些算法。
ad9708 and ad9280 programs, ad collection come again da output, in the middle of some of the algorithms can add their own. (2014-12-16, Others, 6189KB, 下载86次)
用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。
Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction. (2014-06-17, Others, 1597KB, 下载3次)
行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现
Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog (2014-03-20, Others, 1KB, 下载3次)
xs128的程序模拟i2c与24c08通信,令加诺基亚5110 的显示程序,次程序在80m下调试
xs128 process simulation i2c communication with 24c08, so the Canadian Nokia 5110 display program, sub-program under the debugger 80m (2013-08-18, Others, 322KB, 下载12次)
为时尚桌游uno牌计分的小程序，vs写的，源码加执行程序，直接可用
a little program for the card game "uno",which can be used to count the scores during your playing. (2012-04-04, Others, 395KB, 下载9次)
自己编写的通用2维框架结构，可以计算模态、静力、动力响应
A 2D frame building of ANSYS developed by myself, can calculate modal, static and dynamic response
(2010-10-08, Others, 5KB, 下载15次)
本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.
This procedure is a full-adder based on the design of a 16-bit adder, using Verilog HDL language to describe. (2009-05-15, Others, 1KB, 下载4次)
用verilog HDL产生正弦阶梯波。加da即可输出正弦波
Using verilog HDL ladder generated sine wave. Da can increase the output sine wave (2008-07-14, Others, 1KB, 下载26次)
使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG，一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式，采用Load/Store结构，ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算，并支持浮点数加、减、乘、除四种运算，支持与、或、异或、非4种逻辑运算，支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算，支持Load/Store操作，支持地址/立即数加载操作，支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。 (2008-06-02, Others, 42KB, 下载247次)
http://www.pudn.com/Download/item/id/479927.html
基于VHDL硬件描述语言，对基带信号进行MPSK调制（这里M=4）,即QPSK调制
VHDL hardware description language based on the base-band signal MPSK modulation (here M = 4), namely, QPSK modulation (2008-03-16, Others, 1KB, 下载55次)
分布式算法在实现乘加功能时，是通过将各输入数据的每一对应位产生的部分积预先进行相加形成相应的部分积，然后再对各个部分积累加形成最终结果的，而传统算法是等到所有乘积已经产生之后再来相加完成乘加运算的。与传统串行算法相比，分布式算法可极大地减少硬件电路的规模，提高电路的执行速度。
实现一个FIR滤波器，基于分布式算法
输入数据宽度：8位
输出数据宽度：16位
阶数：16阶
滤波器经转换后（右移16位）的特征参数为：
h[0]=h[15]=0000
h[1]=h[14]=0065
h[2]=h[13]=018F
h[3]=h[12]=035A
h[4]=h[11]=0579
h[5]=h[10]=078E
h[6]=h[9]=0935
h[7]=h[8]=0A1F
err (2008-02-18, Others, 1997KB, 下载89次)
3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA
3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA (2007-11-01, Others, 2KB, 下载22次)
2级流水线，使用4元件实现的22位全加器的VHDL语言实现，适用于altera的FPGA
2 lines, use the 4 components realize the full adder 22 of the VHDL language, applicable to altera the FPGA (2007-11-01, Others, 1KB, 下载4次)
本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行
Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim (2007-06-15, Others, 30KB, 下载51次)
用VHDL设计一个4位二进制并行半加器，要求将被加数、加数和加法运算和用动态扫描的方式共阴数码管一同时显示出
VHDL design a four-parallel binary adder, requesting summand, addends and multiplications and dynamic scanning of a total of Yam Digital also showed a (2007-05-12, Others, 1KB, 下载5次)
这是很全的标准库啊，不是1164.vhd，都是一些加，乘，除，平方等操作的包来的．
This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come. (2006-10-21, Others, 80KB, 下载190次)
实现4位加减乘除的alu，采用超前进位加法和布斯乘法，代码较为简单。
achieve four of the ALU arithmetic using CLA Bush and multiplication, code more simple. (2006-01-01, Others, 256KB, 下载13次)