Verilog HDL实现GOST R34.12-2015-一种新的俄罗斯政府标准对称密钥分组密码。
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher. (2017-02-14, Verilog, 12KB, 下载0次)
开放式MSP430是一个用Verilog编写的开源16位微控制器核心，与德克萨斯州...
The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (2022-01-28, Verilog, 22690KB, 下载0次)
GOST 28147-89的Verilog HDL实现-苏联和俄罗斯政府标准对称密钥分组密码
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher (2017-02-14, Verilog, 25KB, 下载0次)
实施32个Verilog迷你项目。32位加法器，阵列乘法器，桶形移位器，二进制除法器16乘8，布斯…
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth … (2022-07-17, Verilog, 0KB, 下载0次)
本项目主要在FPGA上实现了一个经典小游戏“俄罗斯方块”。本项目基本解决方案是，使用Xilinx Zynq系列开发板ZedBoard作为平台，实现主控模块，通过VGA接口来控制屏幕进行显示。
This project mainly realizes a classic game "Tetris" on FPGA. The basic solution of this project is to use the Xilinx zynq series development board zedboard as the platform to realize the main control module and control the screen display through the VGA interface. (2021-03-24, Verilog, 93KB, 下载0次)
伽罗瓦域GF(2^128)乘法器的设计,罗瓦域GF(2^128)乘法器是Ghash算法(一种用于加解密系统散列算法)的核心部件，其速度与硬件开销决定着整个Ghash模块的整体性能
Galois GF (2 ^ 128) multiplier is the core component of ghash algorithm (a hash algorithm used for encryption and decryption system). Its speed and hardware cost determine the overall performance of the whole ghash module (2020-12-17, Verilog, 32082KB, 下载0次)
舍入过程中可以使用直接choping和就近舍入，考虑可就近舍入过程中引起尾码加一导致阶码增加的情况。已通过Quartus_ii\Modelsim的联合仿真。
In the process of rounding, we can use direct choping and nearest rounding, and consider the situation that the tail code plus one leads to the increase of order code. Quartus passed_ II Co simulation of Modelsim. (2020-12-15, Verilog, 7347KB, 下载0次)
用verilog语言设计一位全加器电路，建立符号模块，顶层采用原理图方式设计四位加法器；
The circuit of one bit full adder is designed with Verilog language, and the symbol module is established. The four bit adder is designed by schematic diagram at the top level; (2020-11-08, Verilog, 1531KB, 下载0次)
在可以使蜂鸣器播放音乐的基础上， 增加播放音乐的数量， 要求播放的音乐
在三首以上。
在数码管上显示当前播放的音乐是第几首， 并使播放的音乐在数码管显示屏
上进行滚动（例如，当播放第一首歌曲使，数码管显示 000001，并且 1 由右向
左依次显示，其余位置为 0），当蜂鸣器播放下一首歌时，数码管的显示可以立
即加一，并且仍然由右向左滚动。
On the basis of making the buzzer play music, increase the number of music to be played and the music required to be played
More than three.
In the digital tube display is currently playing the music is the number of, and make the playing music in the nixie tube display screen
For example, when playing the first song, the nixie tube displays 00000 1, and 1 moves from right to right
When the buzzer plays the next song, the display of the nixie tube can stand up
Add one and still scroll from right to left. (2020-07-10, Verilog, 867KB, 下载0次)
本次课程设计的题目是：基于FPGA的竞赛抢答器。
实验要实现的基本功能是 主持人按下开始，三个人抢答，主持人可以给选手加分或者减分，分数用数码管来显示。以下是主要功能和指标：
（1）设计一个可容纳3组参赛的数字式抢答器，每组设一个按钮，供抢答使用。
（2）抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用。
（3）设置一个主持人“复位”按钮。
（4）主持人复位后，开始抢答，第一信号鉴别锁存电路得到信号后，有指示灯显示抢答组别，扬声器发出1~2秒的音响。
（5）设置一个计分电路，每组开始预置10分，由主持人记分，答对一次1分，答错一次减1分。
本次设计内容是通过IES Design Suite14.7和spartan 3E开发板来实现的。
A QIANGDAQI FROM FPGA (2020-06-11, Verilog, 431KB, 下载1次)
MIL-STD1553是一种用于航空电子系统的低速串行总线。参考设计实现了曼彻斯特II的1553所要求的编码和解码以及同步模式的插入和识别，数据序列化和反序列化以及奇偶校验和插入函数。
The MIL-STD-1553 is a low-speed serial bus used in avionics systems. This reference design implements Manchester II encoding and decoding required by the 1553 along with synchronization pattern insertion and identification,data serialization and de-serialization and parity checking and insertion functions. (2018-11-30, Verilog, 32KB, 下载5次)
ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。
Source code of transmission link and reception link of OFDM (2018-11-24, Verilog, 280KB, 下载25次)
DATA_Sramble：扰码模块;DATA_Pilot_Insert：插入导频;data_interleaver：交织器;DATA_CONV_encode：卷积码编码;DATA_16QAM_MAP：调制;CP_ADDER：加循环前缀clock_generator：时钟产生;IFFT：傅立叶反变换;long_training：长训练序列;short_traning：短训练序列;transmit_MCU：主控单元
DATA_Sramble: scrambling block module; DATA_Pilot_Insert: insert pilot; data_interleaver: interleaver; DATA_CONV_encode: convolutional code; DATA_16QAM_MAP: modulation; CP_ADDER: plus cyclic prefix clock_generator: clock generation; IFFT: Fu Liye inverse transform; long_training: long training sequence; short_traning: short training sequence; tra Nsmit_MCU: main control unit (2018-07-29, Verilog, 4734KB, 下载8次)
可计时
可设置一个闹钟
可设置时间
调整分钟或者小时的时候，按键A按一下加一，长按可快进，按键B可减一和快速减，按键C可以清零；
可设置三个小灯提示在调整的是闹钟、小时信号、分钟信号
Set the alarm clock, set the clock, and adjust the time (2018-06-02, Verilog, 1KB, 下载0次)