该项目是一个网络应用程序，旨在帮助基加利一家运输机构的驾驶员在具有中间点的a点到B点的日常路线上导航（在本例中，我使用了卢旺达的地点）。该应用程序利用谷歌地图API提供实时导航和到达每个即将到来的站点的估计时间。
This project is a web application designed to assist drivers for a transportation agency in Kigali in navigating their daily route from Point A to Point B with intermediate points(in this case i used places in Rwanda). The application utilizes the Google Maps API to provide real-time navigation and estimated time to reach each upcoming stop. (2024-04-25, Others, 0KB, 下载0次)
基于同步的数字 复接系统, 即输入的数据码流速率相同。若各 支路 的数 据码 流速 率不 同, 则 不能 直接 进行 复接, 因为复接合成后的数字信 号流, 在 接收端是无法分接恢复成原来的信号的, 为此在复接 前要使各支路数码率同步, 我们可以在设计的同步数字复接系 统前方加一码速调整单元, 以调整各支路的速码率使其同步, 并在分接 后再经过码速调整恢复为原来的速率。
Based on the synchronous digital multiplex system, namely the input data stream rate is the same. If the number of each branch, according to the code flow rate is not directly to pick up, because after the multiplex synthesis of digital signal flow, at the receiving end is unable to connect back to the original signal, so to make the selection in front of the multiplex synchronous digital rate, we can in the design of synchronous digital multiplex system System with a yard in front speed adjustment unit to adjust the selection of speed rate, synchronization and after yards after tapping speed adjust to restore to the original rate. (2015-12-30, Others, 681KB, 下载5次)
基于FPGA的数码管控制程序。旨在通过此程序设计熟悉VHDL程序设计方法与硬件控制方法。
本程序下载后，数码管高两位加计数，低两位减计数，按reset后清零。
FPGA-based digital control procedures. This program is designed to be familiar with VHDL programming design methods and hardware control methods. After this program download, plus two digital high count, the lower two counts down, press the reset is cleared. (2014-11-10, Others, 120KB, 下载2次)
FPGA交通灯说明：
1. 本程序使用VHDL加原理图方式设计而成。
2. 实验时，使用Quartus II软件完成了工程管理与下载验证，使用max+plus II软件进行了功能仿真。
3. 由于实验当时对原理图文件缺乏足够的认识，导致原原理图以及仿真输出文件已经丢失。现在的工程 RTL视图以及仿真输出波形均是在Quartus II软件下得到的。
FPGA traffic lights shows:1procedures for the use of the VHDL schematic design and.In 2 experiments, using Quartus II software to complete the project management and download validation, use max+plus II software to carry out the function simulation.The 3experiment was due to schematic document lacks enough understanding, resulting in the original diagram and simulation output file is missing. Now the engineering RTL view as well as the simulation output waveform are in Quartus II software under. (2012-04-09, Others, 445KB, 下载12次)
数字抢答器① 用EDA实训仪的I/O设备和PLD芯片实现智能电子抢答器的计。
② 智能电子抢答器可容纳4组参赛者抢答，每组设一个抢答钮。
③ 电路具有第一抢答信号的鉴别和锁存功能。在主持人将复位按钮按下后开始抢答，并用EDA实训仪上的八段数码管显示抢答者的序号，同时扬声器发出“嘟嘟”的响声，并维持3秒钟，此时电路自锁，不再接受其他选手的抢答信号。
④ 设计一个计分电路，每组在开始时设置为100分，抢答后由主持人计分，答对一次加10分，答错一次减10分。
⑤ 设计一个犯规电路，对提前抢答和超时抢答者鸣喇叭示警，并显示犯规的组别序号。
① The EDA training instrument I/O devices and PLD chip intelligent electronic Responder count.
② intelligent electronic Responder Responder can accommodate four participants, each with an answer in button.
③ circuit with the first answer in the identification signal and latch functions. The host will begin to answer in the reset button is pressed, and instrument training with EDA eight out digital display on the Responder s serial number, and the speaker issued a "beep" sound, and maintained for 3 seconds, and the circuit from lock, no longer accept other players answer in the signal.
④ design a scoring circuit, at the beginning of each set of 100 points, answer the points after the host, answer a plus 10 points, got it wrong again by 10 points.
⑤ circuit design a foul, the answer in and time out to answer in advance by honking warning, and display groups of foul number.
(2011-06-22, Others, 2143KB, 下载7次)
将写入的数据用曼彻斯特码格式从meout口输出，所需内部存储单元可根据所使用不同的FPGA类型由相应的编译软件产生所需双端口RAM模块
The data will be written by Manchester code format from meout port output, the required internal storage unit can be used according to the different types of FPGA Compiler software from the corresponding dual-port RAM module to generate the required (2010-10-15, Others, 2KB, 下载4次)
ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。
ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor. (2009-08-12, Others, 3KB, 下载110次)
---简化版，实现PCI总线控制---
器件：ep1c6
开发工具：QuartusII
功能：简化PCI总线接口，占用资源少；
实现单路曼彻斯特码的收发。
--- Starter Edition, to achieve control of PCI bus devices---: ep1c6 development tools: QuartusII functions: simplify PCI bus interface, occupy less resources the realization of single-channel transceiver Manchester. (2009-05-06, Others, 166KB, 下载29次)
xilinx设计并完成一个10位的D/F转换器，输入的数字量分别由按键K1,K2来调节，其中K1完成加1功能，而K2则完成减1功能，并把转换的结构西哦女冠到BUZZ蜂鸣器上。
Xilinx design and complete a 10-bit D/F converter, the digital input from the keys K1, K2 to regulate, including the completion of plus 1 functions K1, K2 and completed by 1 functions, and to convert the structure of the West Oh F BUZZ crown to the buzzer on. (2007-12-17, Others, 78KB, 下载71次)
由寄存器,全加器,移位寄存器,计数器,触发器和门电路构成补码一位除法器,将开关设定的补码形式出现的除数,被除数存入相应寄存器中.能用单脉冲按步演示运算全过程.
From the register, full adder, shift register, counters, flip-flops and gates constitute a complement divider will switch set in the form of complement divisor, dividend deposited in the corresponding register. Monopulse can be used by step-by-step demonstration of the entire process of computing. (2007-10-02, Others, 140KB, 下载9次)
Lattice 公 司 把 当 今 两 种 最 新 的 系 统 设 计 技 术，VHDL 和 在 系 统 可 编 程 ( ISP ) 逻 辑 器 件 联 系 在 一 起， 构 成 了isp-VHDl Viewlogic 系 统。isp-VHDL 是 进 行 电 子 系 统 设 计 的 强 有 力 的 工 具， 使 用 它 可 以 加 快 设 计 产 品 投 放 市 场 的 时 间。 isp-VHDL Viewlogic 软 件 能 用 于 各 种 逻 辑 设 计， 这 套 软 件 具 有 功 能 强 大 的 VHDL 综 合、原 理 图 输 入、功 能 与 时 序 仿 真、ispDS+ 适 配 器 和 ispDOWNLOAD 能 力。
two companies today the latest design technology, VHDL and in-system programmable (ISP) logic device linked constitute a isp- VHDl Viewlogic Systems. Isp-VHDL is an electronic system designed powerful tool, It can be used to speed up the design of products on the market in time. Isp-VHDL Viewlogic software can be used for various logic design, This software has powerful VHDL synthesis, diagram entry, functional and timing simulation, ispDS adapter and ispDOWNLOAD capacity. (2006-09-22, Others, 496KB, 下载18次)