DE1-SOC实验开发板和Verilog HDL语言的交互式程序作品，选择避障小车作为课程设计题目，并根据选题制定了如下设计需求：
1.能实现基本的避障小车功能，即躲避障碍，变速，计分，计时显示游戏开始、进行和结束画面；
2.能实现人机交互功能，玩家可通过外接键盘或DE1-SOC开发板自带按键和开关操作小车转向；
3.能通过VGA在显示屏中显示，并且能达到5Hz的刷新频率；
4.能实现自定义小车和障碍物皮肤的功能；
DE1-SOC experiment development board and Verilog HDL language interactive program works. Our group chooses obstacle avoidance car as curriculum design topic, and according to the selected topic, we have designed the following design requirements.
1. can achieve the basic obstacle avoidance car function, that is to avoid obstacles, speed, score, timing display games start, carry out and end the picture;
2. can achieve human-computer interaction function, players can use the external keyboard or DE1-SOC development board to carry button and switch to operate the car.
3. can be displayed in the display screen by VGA, and can reach the refresh frequency of 5Hz.
4. can realize the function of the custom car and the obstacle skin. (2018-03-17, Verilog, 20652KB, 下载26次)
本实验，为 ZX-2 开发板的综合实验，该实验利用 ZX-2 开发板上的 ADC、独
立按键、 UART 等外设， 搭建了一个具备丰富功能的数据采集卡， ZX-2 开发板负
责进行数据的采集并将数据通过串口发送到 PC 机上， PC 端，利用强大的串口调
试工具——串口猎人，来实现数据的接收分析，并将数据分别以波形、码表、柱
状图的形式动态显示出来，以让使用者能够直观的看到 ADC 采集到的信号细节。
同时，用户也可以使用串口猎人通过串口给下位机（ FPGA） 发送指令，下位机将
对接收到的指令进行解码，然后依据解码结果来配置 FPGA 中各个子模块的控制
寄存器，以实现通过串口控制 FPGA 中子模块工作状态的功能。
In this experiment, comprehensive experiment ZX-2 development board, the experimental use ADC ZX-2 development board, separate buttons, UART and other peripherals, to build a feature-rich data acquisition card, ZX-2 Development Board is responsible data collection and data sent via the serial port to the PC, PC side, using powerful serial debugging tools- hunter receives serial analysis to achieve the data and the data waveforms respectively, stopwatch, dynamic histogram form displayed to allow the user to visually see the detail signal ADC collected. At the same time, users can also use serial hunter through the serial port to the next bit machine (FPGA) to send commands, the next crew will have received instruction decode, and then based on the result of decoding to configure the FPGA in each sub-module control registers, in order to achieve through the serial port control FPGA neutron module status functions. (2015-12-01, Windows_Unix, 23824KB, 下载3次)