用VHDL编写的以太网堆栈，
Ethernet stack written in VHDL, (2023-10-09, VHDL, 0KB, 下载0次)
通过Virtex-5 FPGA的嵌入式三模式以太网MAC创建以太网连接。
Creates an Ethernet connection through the embedded Tri-mode Ethernet MAC of the Virtex-5 FPGA. (2011-08-07, VHDL, 966KB, 下载0次)
低速以太网接收发送编码工具，可以讲以太网得数据格式转化为具体得码流
ethernet UDP can generate the data from the ethernet by the tool (2020-11-19, VHDL, 144KB, 下载0次)
RTL8367千兆以太网 交换机的gerber加工文件 原理图，数据手册等
RTL8367 Gigabit Ethernet switch Gerber processing document schematics, data manuals, etc. (2018-06-08, VHDL, 1548KB, 下载80次)
以太网通信verilo实现UDP、TCP传输。
ethernet verilog，udp，tcp (2016-12-23, VHDL, 6228KB, 下载16次)
三速以太网时序约束参考设计，内涵quartus ii 工程，sdc文件
Triple-Speed Ethernet reference design timing constraints, content quartus ii project, sdc file (2016-06-23, VHDL, 3135KB, 下载6次)
光纤模块实现点对点通信，千兆网传输，基于FPGA，采用Verilog语言进行编程，实现千兆网模块的高速传输
Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module (2015-03-17, VHDL, 1085KB, 下载54次)
DE2开发板例程源码，FPGA:EP2C35F256C6，代码基于quartus II 9.0以上的版本（随板光盘的为7.2的版本，在9.0以上的版本上编译通不过会报错）。该代码主要功能为FPGA对以太网通信，与PC机通信
In this demonstration, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. We use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY/MAC Controller. (2014-11-10, VHDL, 1905KB, 下载23次)
非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考
Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference (2013-04-17, VHDL, 688KB, 下载176次)
altera 三速以太网参考设计，verilog源码
Triple Speed Ethernet Data
Path Reference Design (2012-11-02, VHDL, 1770KB, 下载146次)
verilog code for bit stream adapters
verilog code for bit stream adapters (2012-10-29, VHDL, 101KB, 下载4次)
lattice Diamond平台的千兆以太网光纤接口与GMII接口的转换
lattice Diamond Platform of Gigabit Ethernet optical fiber interface and GMII interface conversion (2012-07-02, VHDL, 46KB, 下载38次)
fpga verilog程序，实现诸多模块功能，包括，数码管显示，与ad，da通信，与mcu通信，以便通过mcu将高速ad值显示在lcd显示器上。
fpga verilog program to achieve a number of modules, including, digital display, with the ad, da communication, communication with mcu, mcu high-speed through the ad to the value displayed on the lcd display. (2011-11-13, VHDL, 3536KB, 下载22次)
资料是关于最新Modelsim6.6c使用说明。是从Modelsim官网上面下载的。
Information about the latest Modelsim6.6c instructions. Modelsim official line from the surface of the download. (2010-11-03, VHDL, 2603KB, 下载8次)
利用SOPC Builder搭建三速率以太网基本构架，完成以太网功能。
SOPC Builder using the basic framework set up three speed Ethernet, Ethernet function to complete. (2010-07-30, VHDL, 36633KB, 下载71次)
用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料
Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design (2010-04-03, VHDL, 11KB, 下载205次)
基于verilog编写以太网激励程序源代码
Ethernet-based incentive program write verilog source code (2009-11-11, VHDL, 670KB, 下载24次)
用verilog编写实现的以太网控制器（MAC）源码，解压后用ISE打开工程即可。
Prepared using verilog implementation Ethernet Controller (MAC) source code, open the project after decompression can be used ISE. (2009-11-03, VHDL, 139KB, 下载155次)
以太网控制器MAC的verilog代码，已经过验证，可以用。
Ethernet Controller (2009-05-25, VHDL, 88KB, 下载20次)
Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用。。。
Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . . (2009-04-13, VHDL, 10KB, 下载201次)