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[VHDL/FPGA/Verilog] pn2vhdl

从Petri网到Vhdl
From Petri Nets to Vhdl (2024-03-15, Others, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1710555658215873.html

[VHDL/FPGA/Verilog] verilog_niuke

牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1692452581746852.html

[VHDL/FPGA/Verilog] fpga-stack-network

fpga中的以太网
ethernet in fpga (2019-07-26, C++, 18092KB, 下载0次)

http://www.pudn.com/Download/item/id/1564091815494552.html

[VHDL/FPGA/Verilog] NetFPGA-10G

亿龙网FPGA-10G回购
Yilong s NetFPGA-10G Repo (2015-05-07, Verilog, 59954KB, 下载0次)

http://www.pudn.com/Download/item/id/1431011928592906.html

[VHDL/FPGA/Verilog] nestang

NESTang是一款用Sipeed Tang Nano 20K和Primer 20K板实现的FPGA任天堂娱乐系统
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Nano 20K and Primer 20K boards (2023-05-19, Verilog, 758KB, 下载0次)

http://www.pudn.com/Download/item/id/1684479457237169.html

[VHDL/FPGA/Verilog] verilog-flowgen

以太网流量生成器框架
Ethernet flow generator framework (2015-02-25, Python, 42KB, 下载0次)

http://www.pudn.com/Download/item/id/1424793843728756.html

[VHDL/FPGA/Verilog] pipe25_rc5

pipe可以用于绘制随机petri网和系统性能分析
pipe for help leaner in start stage get more about how to conduct petri net (2018-03-14, LINUX, 2021KB, 下载2次)

http://www.pudn.com/Download/item/id/1521016819398652.html

[VHDL/FPGA/Verilog] LaSaNewNB_M88E1111_TCP1000mhz

用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核
With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core (2018-02-08, Verilog, 18855KB, 下载53次)

http://www.pudn.com/Download/item/id/1518067387875091.html

[VHDL/FPGA/Verilog] timing_constraint

三速以太网时序约束参考设计，内涵quartus ii 工程，sdc文件
Triple-Speed Ethernet reference design timing constraints, content quartus ii project, sdc file (2016-06-23, VHDL, 3135KB, 下载6次)

http://www.pudn.com/Download/item/id/1466646480883662.html

[VHDL/FPGA/Verilog] Dm9000a_Verilog

本文为实现高速数据的实时远程传输处理,提出了采用FPGA直接控制DM9000A进行以太网数据收发的设计思路，实现了一种低成本、低功耗和高速率的网络传输功能，最高传输速率可达100Mbps。
DM9000 driver (2014-11-18, C/C++, 10KB, 下载4次)

http://www.pudn.com/Download/item/id/2657609.html

[VHDL/FPGA/Verilog] ethernet-verilog

非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考
Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference (2013-04-17, VHDL, 688KB, 下载176次)

http://www.pudn.com/Download/item/id/2204973.html

[VHDL/FPGA/Verilog] Lab10

LabVIEW Frequency Analysis in LabVIEW FPGA
LabVIEW Frequency Analysis in LabVIEW FPGA (2013-04-15, LabView, 1886KB, 下载13次)

http://www.pudn.com/Download/item/id/2200662.html

[VHDL/FPGA/Verilog] tse_ref_design

altera 三速以太网参考设计，verilog源码
Triple Speed Ethernet Data Path Reference Design (2012-11-02, VHDL, 1770KB, 下载146次)

http://www.pudn.com/Download/item/id/2035091.html

[VHDL/FPGA/Verilog] BitStream2SPIAdapter

verilog code for bit stream adapters
verilog code for bit stream adapters (2012-10-29, VHDL, 101KB, 下载4次)

http://www.pudn.com/Download/item/id/2030099.html

[VHDL/FPGA/Verilog] fiber_ctrl

lattice Diamond平台的千兆以太网光纤接口与GMII接口的转换
lattice Diamond Platform of Gigabit Ethernet optical fiber interface and GMII interface conversion (2012-07-02, VHDL, 46KB, 下载38次)

http://www.pudn.com/Download/item/id/1927967.html

[VHDL/FPGA/Verilog] Sidge

基于FPGA多串口到以太网网桥的设计与实现
Serial to Ethernet-based multi-FPGA Design and Implementation of bridge (2011-01-26, C/C++, 724KB, 下载15次)

http://www.pudn.com/Download/item/id/1420222.html

[VHDL/FPGA/Verilog] HDLC_VHDL

用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料
Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design (2010-04-03, VHDL, 11KB, 下载205次)

http://www.pudn.com/Download/item/id/1110309.html

[VHDL/FPGA/Verilog] muxsend

调用已绑定的网口发送vlan包。适用于再次开发中遇到网口已被底层绑定的需求。
Call the net mouth has been bound to send vlan packets. For re-development of the net mouth has been encountered in the bottom bound needs. (2010-03-19, Others, 2KB, 下载36次)

http://www.pudn.com/Download/item/id/1092741.html

[VHDL/FPGA/Verilog] ethernet_tri_mode.tar

基于verilog编写以太网激励程序源代码
Ethernet-based incentive program write verilog source code (2009-11-11, VHDL, 670KB, 下载24次)

http://www.pudn.com/Download/item/id/967170.html

[VHDL/FPGA/Verilog] pwm_source

Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用。。。
Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . . (2009-04-13, VHDL, 10KB, 下载201次)

http://www.pudn.com/Download/item/id/713439.html