[以太坊] Ethernet
该项目包括三速以太网、10G以太网（万兆网络基于光口网络协议）和百兆网络端口
The project includes three-speed Ethernet, 10G Ethernet (ten gigabit networks are based on optical port network protocol) and hundred-G network port。 (2024-04-14, VHDL, 0KB, 下载0次)
[collect] LMAC_CORE1
LMAC核心1-以太网1G 100M 10M，
LMAC Core1 - Ethernet 1G 100M 10M, (2023-04-03, VHDL, 0KB, 下载0次)
[VHDL/FPGA/Verilog] EthernetVideo
利用FPGA实现千兆以太网图像传输
Use FPGA to Transfer Image with Gigabits Ethernet (2020-12-02, VHDL, 28613KB, 下载0次)
[VHDL/FPGA/Verilog] miilink
使用以太网RMII连接FPGA和MCU
Connecting FPGA and MCU using Ethernet RMII (2016-01-23, VHDL, 131681KB, 下载0次)
[文章/文档] 基于FPGA的以太网MAC控制器的实现
以太网ＩＥＥＥ８０２．３协议根据ＬＡＮ的特点，把数据链路层分成ＬＬＣ（逻辑链路控制）和ＭＡＣ（介质访问控 制）两个子层．ＭＡＣ层协议作为数据帧收发的基础，是以太网技术的核心，主要负责上层数据和物理层的数据流量 控制和数据流的检测、校验工作．介绍了基于ＦＰＧＡ的１０ＭＨｚ／１００ＭＨｚ以太网ＭＡＣ控制器的设计，整个设计用 Ｖｅｒｉｌｏｇ语言实现
According to the characteristics of LAN, the Ethernet IEEE802.3 protocol divides the data link layer into LLC (logical link control) and MAC (media access control) two sub layer.MAC layer protocol as the basis of data frame transceiver. It is the core of Ethernet technology, mainly responsible for the upper data and physical layer. Data flow control and data flow detection and verification are introduced. The design of 10MHz / 100MHz Ethernet MAC controller based on FPGA is introduced. The whole design is implemented in Verilog language. (2018-05-21, VHDL, 362KB, 下载6次)
[VHDL/FPGA/Verilog] 以太网控制器Verilog源码(含有MAC,MII接口)
使用verilog语言完成MAC层代码的编写
Using the Verilog language to write the code of the MAC layer (2018-03-06, VHDL, 106KB, 下载18次)
[VHDL/FPGA/Verilog] altera-tse-ip
MegaWizard_Plug-In工具生成altera三速以太网IP核并编译仿真
MegaWizard_Plug-In tool to generate altera Triple Speed Ethernet IP Core and compile simulation (2015-04-27, VHDL, 677KB, 下载23次)
[VHDL/FPGA/Verilog] verilog_mac
该文档详细描述了以太网mac层的功能与实现，里面包括了verilog程序
The document describes in detail and implementation of Ethernet MAC layer functions, which includes the Verilog program
(2015-01-13, VHDL, 688KB, 下载8次)
[单片机开发] basics-of-human-Ethernet-interface
本文讲述了以太网接口的基本知识，使初学的人认识和了解以太网接口
This article describes the basics of human Ethernet interface, so that the beginner knowledge and understanding of Ethernet interfaces (2014-06-11, VHDL, 1323KB, 下载5次)
[VHDL/FPGA/Verilog] zs
基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改
Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire project, the frequency of some modules in order to facilitate the simulation piecemeal, behind the notes for the 50mhz crystal divider value can be modified as needed (2013-07-25, VHDL, 874KB, 下载15次)
[VHDL/FPGA/Verilog] actel_fpga_FIFO
actel FPGA的fifo使用说明，你也可以在周立功官网上下载的到，比较实用！
actel FPGA fifo instructions, you can also download form the www.zlgmcu.com ! (2011-08-22, VHDL, 1110KB, 下载14次)
[VHDL/FPGA/Verilog] simple_socket
针对Altera器件所设计的以太网驱动，比官方的好用，速度在20Mbps左右
Altera devices are designed for Ethernet-driven, easy to use than the official speed at about 20Mbps (2011-06-19, VHDL, 500KB, 下载19次)
[VHDL/FPGA/Verilog] Spartan-3E--mac
Spartan 3E开发板中实现以太网通讯
Spartan 3E development board Ethernet communications (2011-06-11, VHDL, 1318KB, 下载36次)
[VHDL/FPGA/Verilog] Libero_UG
libero的使用详细教程，比较详细，比官网上给的教程详细的多
libero use of detailed tutorials, a more detailed tutorial than the official website for more details (2011-05-01, VHDL, 12034KB, 下载49次)
[VHDL/FPGA/Verilog] SDC
quartus官网内总结的sdc有关资料学习
quartus official summary of the net to learn the information sdc (2010-07-22, VHDL, 825KB, 下载154次)
[VHDL/FPGA/Verilog] s3en_udp
基于spartan3e开发板嵌入式EDK开发的UDP协议网口开发程序
EDK embedded development board based on spartan3e UDP protocol developed network port development program (2010-05-13, VHDL, 18293KB, 下载71次)
[VHDL/FPGA/Verilog] 100vhdl
以太网技术入门的好资料，适合初学者和在职工程师
good (2009-08-26, VHDL, 194KB, 下载7次)
[网络编程] AMBA
以太网技术入门的好资料，适合初学者和在职工程师
good (2009-08-26, VHDL, 867KB, 下载12次)
[Windows编程] SDH
他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据
He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data (2009-03-26, VHDL, 6KB, 下载200次)
[VHDL/FPGA/Verilog] k21test
只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。
Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output. (2008-08-19, VHDL, 860KB, 下载47次)