天网数据采集FPGA代码及接口
Skynet Data acquisition FPGA code and interfaces (2012-02-23, Python, 375KB, 下载0次)
使用以太网RMII连接FPGA和MCU
Connecting FPGA and MCU using Ethernet RMII (2016-01-23, VHDL, 131681KB, 下载0次)
VHDL中的小型以太网MAC
Small Ethernet MAC in VHDL (2022-10-09, VHDL, 125KB, 下载0次)
VHDL库用于可合成的最小千兆以太网，具有RGMII接口、最小以太网、ip和udp报头部分...
VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers. (2022-06-04, VHDL, 4259KB, 下载0次)
用于verilog网表的flex+bison解析器
flex+bison parser for verilog netlists (2016-09-28, C++, 4013KB, 下载0次)
以太网交换系统Verilog的验证
Verification of Ethernet Switch System Verilog (2016-10-21, SystemVerilog, 8KB, 下载0次)
Verilog以太网交换机（第2层）
Verilog Ethernet Switch (layer 2) (2021-07-27, Verilog, 147KB, 下载0次)
verilog网表查看器和分析器
verilog netlist viewer and analyzer (2019-08-21, Python, 5KB, 下载0次)
从KiCad网表生成Verilog代码
Generate Verilog code from a KiCad netlist (2023-05-01, Python, 74KB, 下载0次)
使用Verilog编写的管理以太网PHY的MDIO接口的控制器，在小梅哥AC620、AC6102开发板上验证通过，可以成功设置PHY芯片的链接速度到指定的速率。
The controller for managing the MDIO interface of Ethernet PHY written by Verilog has been verified on the development boards ac620 and ac6102 of xiaomeige, and can successfully set the link speed of phy chip to the specified speed. (2020-03-12, Verilog, 3KB, 下载21次)
用FPGA 编写的双端口的RAM，可以实现读写，希望通过这个平台与各个大神交流，希望得到大神的批评指正。
Prepared by FPGA double port RAM, you can read and write, and I hope that through this platform to communicate with the great gods, hoping to get criticism of the great god. (2017-08-10, Verilog, 7227KB, 下载4次)
用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件
Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file (2016-08-22, VHDL, 21945KB, 下载29次)
以太网的verilog的应用软件开发程序，ise开发环境,对于相关设计人员有一定参考价值
Ethernet verilog application software development procedure, ise development environment, has certain reference value for related design personnel (2015-08-29, VHDL, 120KB, 下载4次)
基于fpga的数字频率计，verilog编写，可修改闸门宽度0.1s/1s/10s，可测频率1hz~1mhz，包含整个工程，内部分频模块为了仿真方便改小了，后面注释为50mhz晶振下的分频值，可根据需要自行修改
Fpga-based digital frequency meter, verilog prepared to modify the gate width 0.1s/1s/10s, measurable frequency 1hz ~ 1mhz, contains the entire project, the frequency of some modules in order to facilitate the simulation piecemeal, behind the notes for the 50mhz crystal divider value can be modified as needed (2013-07-25, VHDL, 874KB, 下载15次)
视觉开发模块， 适合采集源自千兆以太网视觉、IEEE 1394、USB摄像头等设备的图像
Vision Development Module, suitable for acquisition from GigE Vision, IEEE 1394, USB video cameras, the image (2012-11-23, Visual C++, 827KB, 下载47次)
24xx02 Verilog Model 在官网上下载的 eepROM
可以参考
Download on the official website 24xx02 Verilog Model eepROM can refer to (2012-11-11, VHDL, 7KB, 下载34次)
在niosii环境下，通过建立SPI核来驱动以太网控制器enc28j60，并通过嵌入tcp/ip协议来实现网口通信。
Niosii environment, through the establishment of the SPI core to drive the Ethernet controller enc28j60 embedded tcp/ip protocol to the network port communications. (2012-07-23, C/C++, 33KB, 下载76次)
用VHDL编写的曼切斯特编解码，适用于以太网上流行的基带传输数字编码。
Manchester encoding and decoding written using VHDL, popular Ethernet baseband transmission of digital coding. (2012-05-25, VHDL, 372KB, 下载16次)
actel FPGA的fifo使用说明，你也可以在周立功官网上下载的到，比较实用！
actel FPGA fifo instructions, you can also download form the www.zlgmcu.com ! (2011-08-22, VHDL, 1110KB, 下载14次)
以太网技术入门的好资料，适合初学者和在职工程师
good (2009-08-26, VHDL, 194KB, 下载7次)