GRETA扩展板适用于Amiga 500计算机，具有快速RAM、microSD大容量存储和以太网控制器，供电...
GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology. (2019-10-12, VHDL, 4425KB, 下载0次)
将图像数据从以太网传输到DDR3,再传输到HDMI进行显示的vivado例程
Vivado routine for transferring image data from Ethernet to DDR3 and then to HDMI for display (2023-02-06, VHDL, 95276KB, 下载3次)
以太网MAC这种三模式全双工以太网MAC子层是用VHDL语言开发的，作为在fpga上使用的商用和免费实现的替代方案。它的主要区别在于注重外部用户界面和内部操作的简单性。只支持基本的以太网功能。core目前只在Xilinx Spartan 6系列FPGA上完全工作。在特伦兹电子设备上通过硬件进行了验证
# 10/100/1000 VHDL Ethernet MAC
This tri-mode full-duplex Ethernet MAC sublayer was developed in VHDL as an alternative to both commercial and free implementations for usage on FPGAs. Its main distinction is the focus on simplicity both in the external user interface and internal operation. Only essential Ethernet functionality is supported.
The core fully works on Xilinx Spartan 6 family FPGAs only at the moment. It was verified on hardware on a Trenz Electronic (2020-12-12, VHDL, 68KB, 下载1次)
Xilinx 以太网接口IP核使用说明文档，可实现SGMII接口，1000BASEX接口等
Xilinx Ethernet interface IP core instruction document, can realize sgmii interface, 1000basex interface, etc (2020-09-27, VHDL, 2054KB, 下载12次)
verilog 实现USB传输功能，包括A/D转换、驱动程序等
vrilog usb (2016-04-19, VHDL, 5047KB, 下载10次)
用于在FPGA中实现图像叠加字幕，字符为FPGA内部rom存储的点阵。
combine word on video stream in FPGA (2015-07-31, VHDL, 2KB, 下载79次)
ethmac10g_latest是用verilog编写的10gbps的以太网mac，对工程开发非常有用！
ethmac10g_latest is written in verilog 10gbps Ethernet mac, very useful for the development of the project! (2015-07-23, VHDL, 771KB, 下载3次)
8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证
8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified (2013-08-22, VHDL, 7KB, 下载175次)
Digilent公司开发板GENESYS板载1Gbps网口实现驱动程序，实现回环模式的发送。
Digilent development board GENESYS onboard 1Gbps ethernet driver, send the loopback mode (2013-07-20, VHDL, 6882KB, 下载13次)
实现88091驱动 带iic驱动 可以通过网管控制盘 通过IIC更新配置参数
Achieve 88,091 iic driver can drive belt through the network control panel update configuration parameters through the IIC (2013-05-31, VHDL, 3KB, 下载2次)
马威尔网卡驱动 交换机驱动 实现8路100M网口交换 实现包自动转发
Marvell LAN Driver 8-way switch drive to achieve 100M Ethernet port switching implementation packages automatically forwarded (2013-05-31, VHDL, 1KB, 下载4次)
XILINX CPLD/FPGA 并口下载线的原理图
XILINX CPLD/FPGA parallel port download cable schematic (2012-09-14, VHDL, 27KB, 下载63次)
基于ｖｈｄｌ的乒乓球比赛设计：用发光二极管作为球，按键为发球和击球，２１分为一局。有５个发光二极管，第三个当做网，过了网才可击球，否则对方加一分，直至有一方达到２１分比赛结束。
Vhdl-based design of table tennis: the light-emitting diode as the ball, the ball and hitting the key for 21 points
For one council. 5 light-emitting diode, the third as a network, over the net before the ball, otherwise the other side plus one straight
To party the end of the game 21 points.... (2012-02-25, VHDL, 2KB, 下载2次)
通过DSP控制CPLD与网口，灯及USB接口芯片的通讯与指示
CPLD and DSP control network through the mouth, lights and USB interface chip communication and instructions (2011-03-08, VHDL, 37KB, 下载6次)
IEEE 802.3u (100Base-T)是100兆比特每秒以太网的标准。100Base-T技术中可采用3类传输介质，即100Base-T4、100Base-TX和100Base-FX，它采用4B/5B编码方式
IEEE 802.3u (100Base-T) is 100 megabits per second Ethernet standard. 100Base-T technology in the transmission medium can be used three categories, namely, 100Base-T4, 100Base-TX and 100Base-FX, which uses 4B/5B encoding (2011-01-07, VHDL, 10KB, 下载54次)
基本的分频器，用于将时钟频率降低一半。包含两个接口，只使用寄存器，未使用线网类型。
The basic divider for halving the clock frequency. Contains two interfaces, using only regs instead of wires. (2010-12-15, VHDL, 1KB, 下载2次)
VHDL数字电路设计教程
乔庐峰等译 当当网销量领先
VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader (2010-08-07, VHDL, 28379KB, 下载25次)
这是有关数字钟的计算机报告，内有源码和DC综合的网表图和时序信息文件。
This is the digital clock of the computer report, with integrated DC-source and netlist file plans and timing information. (2009-05-10, VHDL, 808KB, 下载3次)
这是基于数据包的FIFO，适合于传输系统的设计，例如SDH网。
This is based on the packet FIFO, the transmission system suitable design, such as SDH network. (2009-04-01, VHDL, 2KB, 下载4次)
ISCAS的benchmark 含有原理图，VHDL、VerilogHDL网表，测试数据等。
27-channel interrupt controller
ISCAS the benchmark contains schematic, VHDL, VerilogHDL netlist test data. 27-channel interrupt controller (2008-11-14, VHDL, 38KB, 下载17次)