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Material: 100% Polyester
High Crown
Structured fit
Flat bill
Fitted
Six panel construction with embroidered eyelets
Embroidered graphics
Raised embroidery
Moveable metal pin with enameled graphics
Embroidered fabric appliques
Surface Washable
Officially licensed
Imported
Brand: New Era
Description
Exemplify your impressive Chicago Bulls fandom when you don this dynamic Draft 59FIFTY fitted hat from New Era. It'll be clear to everyone around you on game day that your enthusiastic Chicago Bulls fervor is nothing to be messed with when you sport this fresh cap! (2018-06-08, VHDL, 628KB, 下载1次)
基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫
Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-bit) FPGA using LCMXO2-1200HC-4MG132C clock 25M development board: EEFOUCS little Step (2016-06-28, VHDL, 199KB, 下载6次)
opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。
Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim. (2016-05-03, VHDL, 994KB, 下载7次)
CORTEX-M0处理器官方公开的源代码包！采用模糊网表生成，不可读但可综合可仿真可流片，还有testbench示例，很宝贵的资料！
CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable information! (2014-05-02, VHDL, 1201KB, 下载84次)
altera DE2 开发板的重要应用接口，包括VGA，以太网通信，音频和视频解码，后续开发例程时可以直接使用其中的端口
altera DE2 development board important application interfaces, including VGA, Ethernet communications, audio and video decoding, the subsequent development of routines which can be used directly when the port (2013-08-20, VHDL, 37KB, 下载8次)
这个工程应用于千兆网传输的物理代码子层，同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。
This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36
and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
The differences between the 2 protocols are Link-timer and the control information exchanged during
Auto-negotiation process. (2013-08-08, VHDL, 16183KB, 下载89次)
这是黑金FPGA开发板关于verilog的例程代码，对于初学者是不错的入门资料
This is the black gold FPGA development board routines about verilog code for beginners is a good introductory information (2013-06-30, VHDL, 13024KB, 下载193次)
这是用sopc搭建的一个工程，实现三速以太网的传输。开发版是3c120
This is an engineering sopc structures, triple-speed Ethernet transmission. The Developer Edition is 3c120 (2012-11-13, VHDL, 5217KB, 下载240次)
该代码能实现基于DE-2开发板对88E1111网络接口的访问，是一个较好的代码例子。
The code achieves access 88E1111 internet interface based on DE-2，It is
a good example。 (2012-08-14, VHDL, 26197KB, 下载121次)
88e1111的寄存器的控制，使用verilog，已经调试通过,能够对88e1111操作。
The 88E1111 register control, use verilog, and has been through debugging. (2012-07-07, VHDL, 1KB, 下载524次)
分析：制定规范
设计：状态图，真值表，编写代码。
验证：证明电路的正确性。仿真和形式化验
证。
综合：高层次到低层次转换。生成网表
测试：发现废品。生成测试向量
Analysis: norm design: state diagram, truth table, write the code. Authentication: proof of the correctness of the circuit. Simulation and formal verification. General: High level to low-level conversion. Netlisting test: find waste. Generate test vectors (2011-05-04, VHDL, 196KB, 下载3次)
提出一种适用于数字微波接力系统的基
带光纤拉远的接口方案 采用高性能千兆以太网物理层芯片 88E1111 和 1.25G 光收发器 SSFF3151 完成基带接口
基带信号可以通过数字光纤传输技术传到远端 并恢复射频信号 介绍了 88E1111 的工作原理 性能 接口等 并给出硬件电路设计的原理 以及各部分的具体实现方法和原理图
Compared with the traditional RF and IF pulls distant technology the baseband optical pulls distant technology
has some obvious superiority,especially in feeder line processing and choice of station site it has become the main pulls
distant technology in 3G network such as TD SCDMA.Refering to the baseband optical pulls distant technology in 3G
network the paper proposes a scheme which is suitable for the digital microwave relay system.The design uses high
performance Gigabit chip 88E1111 and 1.25G optical transceiver SSFF3151 to compelete the baseband interface.The signal
transmits to the remote through the digital fiber and restores the radio frequency signal.This paper introduces 88E1111 s
principle performance interface the hardware circuit design principles as well as part of the concrete implementation and
schematic diagrams.The scheme satisfies the baseband transmision in the stability and the error rate aspect.It can be used in
kinds of digital microwave relay systems. (2011-04-12, VHDL, 140KB, 下载137次)
Xilinx公司推荐FPGA培
训教材Xilinx ISE 9.xFPGA/CPLD设计指南的配套光盘内容，每个程序含verilog和VHDL两具版本
Training materials recommended by Xilinx Xilinx ISE 9.xFPGA/CPLD FPGA design guidelines supporting the CD content, each program contains two versions of verilog and VHDL (2011-04-02, VHDL, 8569KB, 下载7次)
介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；
AXI protocol described PPT, and a slave interface is simple to achieve, need to look at (2010-12-10, VHDL, 623KB, 下载461次)
适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。
LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm (2010-03-10, VHDL, 606KB, 下载154次)
适用于10GBase-T的以太网(802.3an协议)LDPC解码器, 用VHDL语言编写，可以应用在LATTICEXP2系列芯片上，基于Gallager算法。
LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm (2010-03-10, VHDL, 864KB, 下载152次)
TLC5510A是一款高速AD转换器，最高可以达到100MBPS，该程序以VHDL实现对TLC5510的控制
TLC5510A is a high-speed AD converter, the maximum can be achieved 100MBPS, the realization of the program to VHDL control of TLC5510 (2009-06-24, VHDL, 1438KB, 下载68次)
本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。
This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform. (2009-03-25, VHDL, 271KB, 下载33次)
链路铜梁调整机制的实现方案，该方案是在MSTP中实现链路容量动态调整的关键技术。是基于SDH中的VCAT，在未来的传送网通信中应用广泛
Link Tongliang realize adjustment mechanism program, which is in MSTP in the link capacity is dynamically adjusted to achieve the key technology. Is based on the SDH in the VCAT, the transmission network in the next letter, a wide range of applications (2008-07-12, VHDL, 13KB, 下载32次)
EPM1270和单片机的8080通讯接口，适合单片机与CPLD之间的高速通讯，verilog语言，QuartusII环境
EPM1270 and 8080 MCU communication interface for MCU and CPLD high-speed communication between, verilog language, QuartusII environment (2008-04-05, VHDL, 472KB, 下载229次)