HDL 描述的模块是软模型， modelsim 仿真的软模型是理想时序。换之，软模型经过综
合器总综合以后就会成为硬模型，也是俗称的网表。而 TimeQuest 分析的对象就是硬模
型的物理时序。用于数字电路设计和ASIC芯片设计
The module described by HDL is a soft model, and the soft model of Modelsim simulation is an ideal timing. In other words, the soft model is integrated
After the combiner is integrated, it will become a hard model, also known as the netlist. The object of timequest analysis is the hard model
The physical timing of type. For digital circuit design and ASIC chip design (2019-11-16, VHDL, 8901KB, 下载2次)
这个CPU是一个简化的专门为教学目的而设计的RISC_CPU。 在设计中我们不但关心 CPU 总体设计的合理性， 而且还使得构成这个RISC_CPU的每一个模块不仅是可仿真的也都可以综合成门级网表。因而从物理意义上说，这也是一个能真正通过具体电路结构而实现的CPU。为了能在这个虚拟的CPU上运行较为复杂的程序并进行仿真, 我们把寻址空间规定为8K（即13位地址线）字节。
This CPU is a simplified RISC_CPU specially designed for teaching purposes. In the design, we not only care about the rationality of the overall design of CPU, but also make every module of RISC_CPU not only simulated, but also integrated into a gate-level network table. Therefore, physically speaking, it is also a CPU that can be realized through specific circuit structure. In order to run more complex programs on this virtual CPU and simulate them, we set the addressing space as 8K bytes (that is, 13-bit address line). (2019-09-22, VHDL, 346KB, 下载0次)
提出了一种32位并行和高度流水线的循环冗余码（CRC）发生器。 该设计可以处理5个不同的通道，每个输入速率为2Gbps（总输出吞吐量为5x4Gbps）。
生成的CRC与32位以太网标准兼容。 该电路已经在0.35Micron标准CMOS工艺中使用标准单元实现，其使用Galois Fields的特性，并且被认为是“自由的”IP。
A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)
The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a free IP. (2017-02-21, VHDL, 439KB, 下载4次)
FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择
FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection (2015-11-18, VHDL, 168KB, 下载20次)
串行UART开源的核心。该设计是专为使用作为一个独立的芯片或用于与其他我们芯的使用。其原因显影串行UART核的事实，即异步串行通信是很常见的，几乎每一个机器理解it.Also，为OCRP-1，我们需要的通信的方式与主计算机，以使它可通过网。
serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net. (2015-09-13, VHDL, 9KB, 下载4次)
基 于 f p g a 的Marvell 88E1111 以 太 网 控 制 器 的 设 计，能发送接收，通过GMII接口实现TCP/UDP 传输
Base on fpga Marvell 88E1111 to mt net control device design, can send and receive, through GMII TCP/UDP transmission on the interface (2015-05-12, VHDL, 2238KB, 下载56次)
“\Example-s5-1\des” 目录下为设计工程，其设计输入采用Synplify预先编译好的.vqm网表
“\Example-s5-1\source”目录下为设计的源代码，这里只给出了Verilog语言实例，仅供读者参考
“\Example-s5-1\source \area_opt”目录下为面积优化的代码
“\Example-s5-1\source \perf_opt”目录下为性能优化的代码
“\Example-s5-1\source \common”目录下是共用的代码
Under \ Example-s5-1 \ des directory for design engineering, the design input using Synplify precompiled .vqm netlist
\ Example-s5-1 \ source directory for the design of the source code, just to give examples of Verilog language, reference work
\ Example-s5-1 \ source \ area_opt directory for the area-optimized code
Under \ Example-s5-1 \ source \ perf_opt directory for performance-optimized code
Under the \ Example-s5-1 \ source \ common directory is shared code (2015-03-09, VHDL, 124KB, 下载5次)
随着电力电子技术的高速发展，工程师们在进行电子设备实际过程中都离不开可靠的电源。开关电源高频化是其发展的方向，高频化使开关电源小型化，并使开关电源进入更广泛的应用领域，特别是在高新技术领域的应用，推动了高新技术产品的小型化、轻便化。另外开关电源的发展与应用在节约能源、节约资源及保护环境方面都具有重要的意义。 为了帮助工程师解决这方面的难题，OFweek电子工程网整合设计资源特别推出《开关电源设计实例指南》电子书，希望这本电子书和以前推出的电子书一样可以帮助本土工程师的设计创新。
good power design book (2014-05-28, VHDL, 7671KB, 下载5次)
MPI接口就是CPU和逻辑之间通信的一个接口，一般使用总线方式，总线一般有两种标准，一种是MOTO模式，另外一种是intel模式。本资料包含verilog程序以及说明
MPI interface is an interface for communication between the CPU and logic, the general way of using the bus, the bus there are two standards, one is the MOTO mode, the other one is the intel mode. This information contains verilog procedures and instructions (2014-04-28, VHDL, 120KB, 下载6次)
8B10B是应用最广泛的编码技术。它被用于串行连 接SCSI、串行ATA、光纤链路、吉比特以太网、XAUI（10吉比特接口）、PCIExpress总线、InfiniBand、 SeriaRapidIO、HyperTransport总线以及IEEE1394b接口（火线）技术中。
8b/10b has been widely adopted by a variety of high speed data communication standards
used today and should prove ever more useful for FPGA-based designs as clock speeds and
I/O capabilities increase.
8b/10b has been widely adopted by a variety of high speed data communication standards
used today and should prove ever more useful for FPGA-based designs as clock speeds and
I/O capabilities increase. (2012-05-22, VHDL, 3KB, 下载10次)
随着多微机系统的应用和微机网络的发展，通信功能越来越显得重要。串行通信是在一根传输线上一位一位地传送信息.这根线既作数据线又作联络线。串行通信作为一种主要的通信方式，由于所用的传输线少，并且可以借助现存的电话网进行信息传送，因此特别适合于远距离传送。在串行传输中，通信双方都按通信协议进行，所谓通信协议是指通信双方的一种约定。约定对数据格式、同步方式、传送速度、传送步骤、纠错方式以及控制字符定义等问题做出统一规定，通信双方必须共同遵守。
With the application of multi-microcomputer systems and computer networks, communication becomes less important. Serial communication is a one in a transmission line to transmit information, which lines both for the data line and make contact line. Serial communication as a primary means of communication, since the transmission line with less, and can make use of existing telephone network for information transmission, it is particularly suitable for long-distance transmission. In serial transmission, the communication protocol for communication by both sides, the so-called communication protocol is an agreement the two sides. Agreement on data formats, synchronization, transmission speed, transmission procedures, error correction, and control characters are defined to make uniform provisions and other issues, communication, both parties must abide by. (2011-11-01, VHDL, 1KB, 下载2次)
本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡，它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件，可以控制电脑灯或者其他DMX512协议的设备，比如LED灯、激光灯、PAR灯、DJ设备等等。
本系统还有体积小巧携带方便等特点，足够一般的娱乐场所、多功能厅、会议厅等场所使用，同时采用电脑进行灯光的控制，也可以提升工程的技术含量，显得更高科技。通过简单更改DMX模块的UART部分，还可以将串口转换usb接口，不过由于手头上的FPGA开发板没有USB接口，所以使用UART接口进行测试。
The system design using FPGA, a serial port on the computer then a DMX512 protocol adapter, it can make your computer into a super computer console or lighting console lights, LED controller. Through computer software, can control lights or other DMX512 protocol computer equipment, such as LED lights, laser lights, PAR lamps, DJ equipment. The system also features compact, portable and so on, is sufficient for most of the entertainment, function rooms, conference rooms and other places to use, while using computer control of lighting can also enhance the project s technical content, appears to higher technology. DMX module by simply changing the UART portion can also convert usb serial interface, however, because the FPGA development board on hand no USB interface, so tests using the UART interface.
(2010-07-11, VHDL, 2171KB, 下载270次)
verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等
verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other (2009-12-19, VHDL, 12KB, 下载420次)
两人乒乓球游戏机能够模拟乒乓球比赛的基本过程和规则，并能自动裁判和记分。乒乓球游戏机是用8个发光二极管代表乒乓球台，中间两个发光二极管兼做乒乓球网，用点亮的发光二极管按一定的方向移动表示球的运动。在游戏机的两侧设计两个开关，一个是发球一个是击球。甲乙两人按乒乓球比赛的规则来操作开关，数码管做计分牌，自动计分。
The two table tennis table tennis game can simulate the basic processes and rules, and can automatically judge and score. Table tennis game is eight light-emitting diodes on behalf of table-tennis table, table tennis, also cater to the middle of two light-emitting diode networks, with the light-emitting diode according to a certain move that the ball movement. In the game on both sides of the design of two switches, one is one shot off the tee. Both A and B according to the rules of table tennis competition to operate the switch, the digital control to do scoreboard, automatic scoring. (2009-11-16, VHDL, 2KB, 下载132次)
本帖最后由 NovaCao 于 1-18-2009 18:02 编辑
使用Quartus II进行仿真
QQ：44425312
QQ群：50585234（群名称：FPGA4u）
gtalk：fpgaforu@gmail.com
网站：www.fpga4u.com
淘宝网店：http://shop34914329.taobao.com/
我们以一个计数器为例，在QuartusII中对其进行仿真。
打开Quartus II，新建一个工程，新建Verilog HDL文件
This quote was last NovaCao on 1-18-2009 18:02 by editing the use of Quartus II simulation QQ: 44425312 QQ Group: 50,585,234 (group name: FPGA4u) gtalk: fpgaforu@gmail.com Website: www.fpga4u.com Taobao shop : http://shop34914329.taobao.com/ us to a counter example, in QuartusII in its simulation. Open the Quartus II, create a new project, the new Verilog HDL files (2009-11-07, VHDL, 5KB, 下载2次)
本帖最后由 NovaCao 于 1-18-2009 18:02 编辑
使用Quartus II进行仿真
QQ：44425312
QQ群：50585234（群名称：FPGA4u）
gtalk：fpgaforu@gmail.com
网站：www.fpga4u.com
淘宝网店：http://shop34914329.taobao.com/
我们以一个计数器为例，在QuartusII中对其进行仿真。
打开Quartus II，新建一个工程，新建Verilog HDL文件
This quote was last NovaCao on 1-18-2009 18:02 by editing the use of Quartus II simulation QQ: 44425312 QQ Group: 50,585,234 (group name: FPGA4u) gtalk: fpgaforu@gmail.com Website: www.fpga4u.com Taobao shop : http://shop34914329.taobao.com/ us to a counter example, in QuartusII in its simulation. Open the Quartus II, create a new project, the new Verilog HDL files (2009-11-07, VHDL, 5KB, 下载11次)
我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ
Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ (2009-08-03, VHDL, 115KB, 下载846次)
设计一个乒乓球游戏机，该机模拟乒乓球比赛的基本过程和规则，并能自动裁判和计分。
1、 使用乒乓球游戏机的甲乙双方各在不同的位置发球或击球。
2、 乒乓球的位置和移动方向有灯亮及依次点燃的方向决定，球移动的速度为0.1~0.5S移动一位。使用者根据球的位置发出相应的动作，提前击球或出界均判失分。设计者可按过网击球来设计，也可按乒乓球移动到对方第二盏灯亮后方可击球来设计。
3、 比赛用21分为一局来进行，甲乙双方都应设置各自的计分牌，任何一方先计满21分，该方就算赢了此局。当计分牌清零后，又可开始新的一局比赛。
The design of a table tennis game, it' s the basic table tennis simulation process and the rules and referees and scoring automatically. (2009-05-23, VHDL, 1KB, 下载47次)
Xilinx ISE中文简明教程、Xilinx术语中文.pdf、Virtex 系列 FPGA 的配置和回读、FPGA设计检查清单.pdf、设计注意.pdf、逻辑设计注意列表.pdf
Xilinx ISE Chinese Concise Guide, Xilinx Chinese terminology. Pdf, Virtex Series FPGA configuration and read-back, FPGA design checklist. Pdf, design attention. Pdf, logic design attention to the list. Pdf (2008-09-17, VHDL, 1924KB, 下载1441次)
超低速的光纤一体发接收发送器,同于以前的光纤一体化接头都只适用于2M以上的通讯,如需将232等低速信号用光纤传输出,需要加复杂的调制解调电路,网动光电新生产的这款光纤头主要针对低速信号,可以传送DC-500KPS的信号,极大地简化了硬件设计.
Ultra-low-fat whole-speed fiber-optic transmitter receiver with fiber-optic integration in the previous joint only applies to more than 2M communications, etc. For the 232 low-speed optical fiber transmission of signals, the need to increase the complexity of the modulation and demodulation circuit, the net move Photoelectric new production of this first major response to low-speed fiber-optic signal, DC-500KPS can send the signal, greatly simplifying the hardware design. (2008-06-27, VHDL, 94KB, 下载42次)