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按分类查找All VHDL/FPGA/Verilog(560) 

[VHDL/FPGA/Verilog] AdderNet-FPGA

加法器网FPGA,,
AdderNet-FPGA,, (2021-03-03, VHDL, 22786KB, 下载0次)

http://www.pudn.com/Download/item/id/1614748671205772.html

[VHDL/FPGA/Verilog] Verilog2Spice

结构简单的VERILOG网表到SPICE网表转换器
Simple strutured VERILOG netlist to SPICE netlist translator (2022-05-22, Python, 4KB, 下载0次)

http://www.pudn.com/Download/item/id/1653204931883146.html

[VHDL/FPGA/Verilog] ethernet_mii_udp_1

Verilog开发的,MII接口的百兆以太网UDP代码
100 megabit Ethernet UDP code of MII interface (2020-03-20, Verilog, 3820KB, 下载26次)

http://www.pudn.com/Download/item/id/1584692361215646.html

[VHDL/FPGA/Verilog] adc

fpga controlled adc 7768
fpga controlled adc 7768 (2019-06-28, VHDL, 960KB, 下载0次)

http://www.pudn.com/Download/item/id/1561725156409503.html

[VHDL/FPGA/Verilog] Chapter10 Sample

实现以太网功能,全部文件都包括,可以直接下载使用
Ethernet project file (2018-07-03, Verilog, 140KB, 下载2次)

http://www.pudn.com/Download/item/id/1530577591803720.html

[VHDL/FPGA/Verilog] Transmit_subsystem-master

千兆以太网的相关资料,包括相关的一些测试文件
Gigabit Ethernet related information (2018-03-16, Verilog, 2631KB, 下载1次)

http://www.pudn.com/Download/item/id/1521161229257703.html

[VHDL/FPGA/Verilog] ethmac10g

千兆以太网设计,包括组包解包,可以实现大数据传输功能。
Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function. (2017-04-19, VHDL, 843KB, 下载16次)

http://www.pudn.com/Download/item/id/1492610362896926.html

[VHDL/FPGA/Verilog] xge_mac_latest.tar

用Verilog编写的以太网控制器,可以使用,里面是全部verilog源码
Ethernet controller based on Verilog, can be used directly, all verilog files (2015-12-21, VHDL, 1102KB, 下载5次)

http://www.pudn.com/Download/item/id/1450689171650289.html

[VHDL/FPGA/Verilog] Txd

1000M以太网媒体介入控制器EMAC的传输部分的源代码
1000M ethnet transmiter (2014-03-13, VHDL, 171KB, 下载4次)

http://www.pudn.com/Download/item/id/2482924.html

[VHDL/FPGA/Verilog] ethernet.tar

verilog写的以太网硬件模型,使用xilinx FPGA,ieee802.3ae
an ethernet model in Verilog,using a Xilinx FPGA,and the function:IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation (2013-10-11, VHDL, 770KB, 下载35次)

http://www.pudn.com/Download/item/id/2372157.html

[VHDL/FPGA/Verilog] no_ip_core_eth

没有使用三速以台湾IP核实现以太网数据的接收
Taiwan did not use three-speed Ethernet IP core data reception (2013-08-02, VHDL, 4782KB, 下载4次)

http://www.pudn.com/Download/item/id/2320347.html

[VHDL/FPGA/Verilog] 8155-PB00-R

FPGA实现100G以太网传输外围扩展协议芯片BCM8155技术资料
FPGA implementation of 100G Ethernet transmission protocol chip BCM8155 peripheral expansion technical information (2013-06-14, Windows_Unix, 120KB, 下载3次)

http://www.pudn.com/Download/item/id/2279003.html

[VHDL/FPGA/Verilog] fsl_net

基于FSL总线的以太网控制器,用于Microblaze系统
Ethernet controller based on FSL bus (2013-06-04, Others, 9KB, 下载5次)

http://www.pudn.com/Download/item/id/2269262.html

[VHDL/FPGA/Verilog] W5300

W5300简单百兆网开发资料,方便MCU与网口的通信
W5300 Simple Fast network development information, facilitate communication MCU with Ethernet port (2013-03-14, VHDL, 2186KB, 下载200次)

http://www.pudn.com/Download/item/id/2158908.html

[VHDL/FPGA/Verilog] ethernet

lwip实现简单的收发包的以太网工程。基于FPGA的板子
realization of a simple packet transceiver procedures. FPGA-based board (2012-10-30, C/C++, 4982KB, 下载17次)

http://www.pudn.com/Download/item/id/2031621.html

[VHDL/FPGA/Verilog] ethernet_tri_mode

三速以太网接口模块verilog源码和测试
Triple-speed Ethernet interface module verilog source code and test (2012-06-06, VHDL, 3018KB, 下载49次)

http://www.pudn.com/Download/item/id/1904282.html

[VHDL/FPGA/Verilog] ethernet(MAC)verilog-langue

用veriolog编写以太网控制器(MAC)
ethernet MAC of verilog (2012-02-29, VHDL, 135KB, 下载63次)

http://www.pudn.com/Download/item/id/1782364.html

[VHDL/FPGA/Verilog] openPOWERLINK_openMAC_v1.5.9.6

powerlink工业以太网协议FPGA解决方案,
FPGA of powerlink protocol (2010-10-13, Unix_Linux, 920KB, 下载126次)

http://www.pudn.com/Download/item/id/1316370.html

[VHDL/FPGA/Verilog] eth

一个ahb接口的千兆以太网MAC,包括apb的配置接口
Ahb a Gigabit Ethernet interface MAC, including the configuration interface apb (2010-03-17, VHDL, 31KB, 下载87次)

http://www.pudn.com/Download/item/id/1090007.html

[VHDL/FPGA/Verilog] MAIN_TX_V10

8路视频光端机的VHDL源码,此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。
8-channel video PDH in VHDL source code (2009-09-04, VHDL, 284KB, 下载150次)

http://www.pudn.com/Download/item/id/900708.html
总计:560