[VHDL/FPGA/Verilog] snestang
用于Tang Primer 25K FPGA的超级任天堂娱乐系统
Super Nintendo Entertainment System for Tang Primer 25K FPGA (2024-01-07, SystemVerilog, 0KB, 下载0次)
[VHDL/FPGA/Verilog] src
以太网MAC数据链路层，在FPGA内用Verilog语言实现对应功能
Ethernet MAC layer,in FPGA, implement this function with verilog language (2018-08-07, Verilog, 60KB, 下载3次)
[VHDL/FPGA/Verilog] ethernet_loopback
通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算
Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation (2017-11-20, Verilog, 23381KB, 下载43次)
[VHDL/FPGA/Verilog] pc_fpga_com_latest.tar
用VHDL实现的PC与FPGA之间的网络通信，通过以太网进行通信
comunicate between PC and FPGA via ethernet (2017-04-26, VHDL, 183KB, 下载6次)
[VHDL/FPGA/Verilog] my_alu
一个简单的ALU程序设计，实现以下功能：
逻辑运算：与、或、非、异或、逻辑左移、逻辑右移
算术运算：加、减
A simple ALU program designed to achieve the following functions: logic operations: AND, OR, NOT, XOR logical left, logical shift right arithmetic operations: addition, subtraction (2016-05-03, Others, 580KB, 下载1次)
[VHDL/FPGA/Verilog] Ethernet_Accel_Design
altera官方以太网例程（基于niosII）
Accelerating Nios II Ethernet Applications
User Guide
(2014-07-21, VHDL, 2593KB, 下载38次)
[VHDL/FPGA/Verilog] cheap_ethernet_latest.tar
用fpga实现的以太网ip协议，能实现1000m的速度，实现简单！
ip vhdl (2014-07-08, VHDL, 505KB, 下载12次)
[VHDL/FPGA/Verilog] 7_lan
FPGA 网口通信驱动 采用寄存器操作 已经通过验证
FPGA driver for lan port，operating on rejisters，tested successfully (2014-05-10, C/C++, 6KB, 下载9次)
[VHDL/FPGA/Verilog] FPGADM9000AVerilog
FPGA控制DM9000A进行以太网数据收发的Verilog实现
FPGA control DM9000A Ethernet data transceiver Verilog realize (2013-11-27, VHDL, 4102KB, 下载14次)
[VHDL/FPGA/Verilog] 10_100m_ethernet-fifo
本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。
The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion. (2012-07-10, Others, 476KB, 下载8次)
[VHDL/FPGA/Verilog] DE2_NET
基于altera的DE2开发板的以太网设计成功例程
Successful routine altera DE2 board Ethernet design
(2012-04-24, VHDL, 1785KB, 下载47次)
[VHDL/FPGA/Verilog] verilog-mac
这是一个以太网的mac程序，verilog写的，可方正 可实现
this is a mac implementation using verilog，you can emulate it or implement it directly (2012-01-07, Windows_Unix, 125KB, 下载129次)
[VHDL/FPGA/Verilog] ethernet10-100M-IP-core
以太网10-100M IP核Verilog源码，可综合
Ethernet 10-100M IP core Verilog source code can be integrated (2011-07-08, VHDL, 723KB, 下载21次)
[VHDL/FPGA/Verilog] MACtop
基于FPGA的以太网控制器（MAC）源码，包括发送、接收、控制、CRC、寄存器、计数器等模块
Ethernet MAC sub-layer protocol (2011-05-01, VHDL, 125KB, 下载153次)
[VHDL/FPGA/Verilog] ethernet_controller_Verilog
以太网控制器源码，verilog语言,包含MAC、MII接口
Ethernet controller ,include MAC and MII interfaces ,by verilog (2010-09-26, Visual C++, 70KB, 下载200次)
[VHDL/FPGA/Verilog] HDLC_E1
E1到HDLC转换 实现E1到以太网
E1到HDLC转换 实现E1到以太网
E1 TO HDLC E1 TO ETHETH
(2010-01-21, VHDL, 439KB, 下载161次)
[VHDL/FPGA/Verilog] FPGA-DM9000A
FPGA控制DM9000A进行以太网数据收发的Verilog实现
FPGA control DM9000A for Verilog realization of Ethernet data sent and received (2010-01-17, VHDL, 2596KB, 下载457次)
[VHDL/FPGA/Verilog] FPGAcontrolDM9000AuseVerilog
verilog控制以太网发送程序的实现，用于控制以太网发送
verilog control program for sending Ethernet implementation, used to control the Ethernet to send (2009-08-30, VHDL, 4KB, 下载71次)
[VHDL/FPGA/Verilog] ethernet_example
FPGA上实现以太网 用VHDL实现，欢迎多交流
FPGA to achieve the realization of Ethernet using VHDL welcome more exchanges (2008-12-25, C/C++, 193KB, 下载71次)
[VHDL/FPGA/Verilog] ethernet__verilog
fpga模拟以太网物理层的源代码，用verilog硬件描述语言开发。
FPGA simulation of the Ethernet physical layer of the source code, using Verilog hardware description language development. (2007-09-08, Others, 323KB, 下载307次)