实现100M到1G以太网通信，包括收发模块，PHY模块。
Realize 100M to 1G Ethernet communication, including transceiver module and PHY module. (2019-04-25, Verilog, 14266KB, 下载13次)
基于Xilinx Spartan-6开发板，实现以太网通信
Ethernet communication (2018-02-26, Verilog, 24616KB, 下载7次)
基于xilinx 厂商的FPGA硬件的开发源代码，包括UART,SPI,以太网通信等等
The development of FPGA hardware based on xilinx manufacturers source code, including the UART, SPI, Ethernet communication and so on (2016-08-22, VHDL, 16724KB, 下载11次)
在xilinx用verilog实现工业以太网的全部文件
industrial ethernet in xilinx (2016-05-31, VHDL, 3294KB, 下载10次)
FPGA控制DM9000A进行以太网数据收发的Verilog实现
FPGA control DM9000A Ethernet data transceiver Verilog realize (2014-07-28, VHDL, 2735KB, 下载41次)
采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输
Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed (2014-03-06, VHDL, 4714KB, 下载155次)
FPGA 100M以太网UDP/IP收发
FPGA 100M Ethernet UDP/IP to send and receive (2014-01-16, VHDL, 2135KB, 下载109次)
用数字逻辑语言描述以太网，百兆以太网MAC和MII的verilog源码
With digital logic language to describe Ethernet (2013-09-24, VHDL, 121KB, 下载13次)
本文基于xilinx fpga ，v5,主要介绍如何用FPGA制作以太网
Based xilinx fpga, v5, describes how to use the FPGA making Ethernet (2013-01-23, VHDL, 2336KB, 下载139次)
XILINX的一个以太网例程，包含以太网内核的建立以及仿真过程，是XAPP443的例子
Routines of the XILINX a Ethernet, including Ethernet kernel establish and simulation process XAPP443 example (2013-01-10, VHDL, 9449KB, 下载19次)
Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。
Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet. (2012-07-22, Visual C++, 886KB, 下载42次)
以太网芯片dm9000a测试，程序配置了DM9000a，使该芯片完成以太网口的数据发送。
The Ethernet chips DM9000A test, the program is configured DM9000a, allows the chip to complete the Ethernet port to send data. (2012-05-17, VHDL, 9372KB, 下载8次)
xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供
xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official (2011-08-29, VHDL, 10KB, 下载124次)
SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。
SDR SDRAM controller from Altera (2011-08-28, VHDL, 2305KB, 下载113次)
MII接口编程,用于收发以太网MAC帧的FPGA实现。
MII interface programming, send and receive Ethernet MAC frame for the FPGA. (2011-04-27, VHDL, 3KB, 下载111次)
清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。
Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it. (2010-09-26, VHDL, 4KB, 下载113次)
MAC(以太网媒体访问控制)是以太网IEEE 802.3协议规定的数据链路层的一部分,使用FPGA替代ASIC,实现以太网MAC功能非常实用。能够实现硬件系统多路多端口的以太网接入,并在自行开发需要以太网接入的嵌入式处理器设计中得到应用。具体探讨以太网MAC的功能定义,使用FPGA实现以太网MAC的方法,对以太网的相关应用设计具有指导作用。
MAC (Ethernet Media Access Control) is a protocol under the IEEE 802.3 Ethernet data link layer part of the use of FPGA alternative ASIC, Ethernet MAC functionality is very useful. Hardware system to achieve multi-channel multi-port Ethernet access and Ethernet access to its own development needs of embedded processor design has been applied. To specifically explore the functional definition of the Ethernet MAC using FPGA Ethernet MAC method, the design of Ethernet-related applications guide. (2010-03-26, VHDL, 1536KB, 下载188次)
以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档
Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents (2009-10-21, VHDL, 825KB, 下载230次)
利用ALTERA公司Cyclone II 2C35 fpga芯片，实现以太网通信。以太网芯片为DM9000A
ALTERA companies use Cyclone II 2C35 fpga chips, Ethernet communications. Ethernet chips DM9000A (2008-09-12, VHDL, 538KB, 下载237次)
具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述
With GMII interface and feature ARP protocol Gigabit Ethernet controller. After Xilinx SPATAN-III FPGA verification, Verilog description (2008-03-04, MultiPlatform, 68KB, 下载723次)