使用MIPS32架构的RISC处理器
RISC Processor Using MIPS32 Architecture (2024-01-16, Verilog, 0KB, 下载0次)
微处理器和嵌入式系统
Microprocessor and Embedded systems (2023-11-01, Verilog, 0KB, 下载0次)
32位定点嵌入式3D图形处理器，
32-bit Fixed-Point Embedded 3D Graphics Processor, (2023-10-09, Verilog, 0KB, 下载0次)
MIPS 4级流水线处理器，，
MIPS 4 Stage Pipelined Processor,, (2023-09-09, Verilog, 0KB, 下载0次)
使用verilog、、的多级非流水线MIPS处理器，，
Multi-stage-non-pipelined-MIPS-processor-using-verilog,, (2022-03-09, Verilog, 0KB, 下载0次)
这是一个简单的RISC 32位流水线处理器，也没有使用MIPS ISA在Verilog中制作的流水线处理器。，
This is a simple RISC 32 bit pipelined as well as without pipelining processor made in Verilog using MIPS ISA., (2022-09-17, Verilog, 0KB, 下载0次)
数字逻辑与微型处理器设计课程设计,6级流水线 mips 处理器,可以进行 行列交织,卷积运算,
Course design of digital logic and microprocessor design, 6-level pipelined mips processor, which can perform row column interleaving and convolution operation, (2021-03-09, Verilog, 0KB, 下载0次)
32位通用整数微处理器，
32-bit general purpose integer microprocessor, (2022-08-22, Verilog, 0KB, 下载0次)
单周期 mips 指令集处理器,
Single cycle mips instruction set processor, (2020-12-13, Verilog, 0KB, 下载0次)
Verilog HDL中MIPS处理器的设计，
Design of a MIPS processor in Verilog HDL, (2019-03-23, Verilog, 0KB, 下载0次)
Mips单周期处理器；用verilog.编码。，
Mips Unicycle Processor; coded in verilog., (2018-04-30, Verilog, 0KB, 下载0次)
具有附加操作的Mips lite处理器，
Mips lite processor with additional operation, (2023-01-13, Verilog, 0KB, 下载0次)
使用Verilog的MIPS 32处理器架构设计，
MIPS 32 Processor Architecture design using Verilog, (2022-08-07, Verilog, 0KB, 下载0次)
在Verilog中实现的流水线MIPS处理器，
A pipelined MIPS processor implemented in Verilog, (2021-01-12, Verilog, 0KB, 下载0次)
32位单周期mips处理器，
32-bit single cycle mips processor, (2023-02-19, Verilog, 0KB, 下载0次)
32位2级流水线MIPS处理器，
32 Bits 2-stage pipeline MIPS processor, (2021-12-01, Verilog, 0KB, 下载0次)
用于31条指令的朴素MIPS模拟器。，
A naive MIPS simulator for 31 instructions., (2020-09-27, Verilog, 0KB, 下载0次)
配备内聚危险检测单元、转发单元和控制器的5级管道处理器。由我用Verilog HDL编写...，
Complete 5 stage pipeline proccessor with a cohesive hazard detection unit, forwarding unit, and controller. Written by me in Verilog HDL. Loaded instruction memory of MIPS ISA converted from C code written and converted by me. (2021-03-10, Verilog, 0KB, 下载0次)
经典的5级流水线MIPS 32位处理器，包括2位分支预测器、分支预测缓冲区和直接映射缓存。，
A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache., (2017-12-29, Verilog, 0KB, 下载0次)
can总线控制器的IP核，可直接用于soPC中
The IP core of the CAN bus controller can be directly used in soPC. (2018-08-26, Verilog, 59KB, 下载8次)