综合verilog解析器
synthesized verilog parser (2024-01-24, Verilog, 0KB, 下载0次)
FPGA视频缩放器,,
FPGA videoScaler,, (2023-10-27, Verilog, 0KB, 下载0次)
基于FPGA_CNN_加速器,
FPGA-based_CNN_Accelerator, (2023-10-24, Verilog, 0KB, 下载0次)
MIPS处理器的所有子模块(指令存储器、数据存储器、ALU等)的RTL Verilog文件,然后实现top mo...,
the RTL Verilog files for all sub-modules of the MIPS processor (Instruction memory, data memory, ALU, etc.) then implementing the top module of MIPS processor. (2023-10-05, Verilog, 0KB, 下载0次)
在该项目中,8种不同的Verilog HDL D触发器(DFF)实现,包括上升沿触发器和下降沿触发器、同步...,
In this project, 8 distinct Verilog HDL implementations of D flip-flops (DFFs), encompassing rising and falling edge triggers, synchronous and asynchronous resets are designed. (2023-08-09, Verilog, 0KB, 下载0次)
fpga运动控制器
fpga motion controller (2019-07-10, Verilog, 22KB, 下载2次)
FPGA毛刺器基于无齿公司的艺术毛刺器,但适用于破冰船
FPGA glitcher based on toothlessco s arty-glitcher, but for the icebreaker (2019-12-10, Verilog, 26KB, 下载0次)
便携式RISC-V片上系统实现:RTL、调试器和模拟器
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators (2023-05-28, Verilog, 30715KB, 下载0次)
基于Verilog的NoC模拟器
Verilog-Based-NoC-Simulator (2016-05-04, Verilog, 124KB, 下载0次)
处理器回购
Processor repo (2013-12-19, Verilog, 23KB, 下载0次)
一位带进位的十进制计数器,包括计数器模块,LED驱动模块和按键消抖模块,进行了计数器封装,功能仿真,管脚约束,FPGA下载文件测试。
A decimal counter with carry, including counter module, LED driver module and key anti shake module, has carried out counter packaging, function simulation, pin constraint, FPGA download file test. (2021-04-18, Verilog, 2713KB, 下载0次)
一个用硬件描述语言verilog实现的同步清零的模55计数器。
A module 55 counter of synchronous zero clearing realized by Verilog. (2020-04-14, Verilog, 576KB, 下载1次)
基于FPGA的温度传感器的读操作Verilog代码
Read operation code of temperature sensor based on FPGA (2018-08-18, Verilog, 11035KB, 下载11次)
利用EDA设计加法器减法器,结合数电知识
Using EDA to design adder subtracting device, combined with digital knowledge. (2018-05-29, Verilog, 23KB, 下载1次)
Verilog的135个经典设计实例,部分摘录如下:【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】(7,4)循环码纠错译码器【例 12.10】(7,4)线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。
135 classic examples of Verilog design (2018-04-25, Verilog, 164KB, 下载3次)
多周期流水线处理器的verilog实现。
The Verilog implementation of a multi cycle pipelined processor. (2018-02-24, Verilog, 14231KB, 下载37次)
fir滤波器的简单实现,主要用于学习与理解
Simple implementation of the fir filter, mainly for learning and understanding (2018-02-03, Verilog, 1KB, 下载8次)
实现两个数字的比较大小,包括顶层文件和源文件以及测试文件。
To achieve the size of the two figures. (2017-11-12, Verilog, 1KB, 下载1次)
产生8bit随机数,采用线性反馈移位寄存器
The 8bit random number is generated by using linear feedback shift register (2017-11-06, Verilog, 99KB, 下载3次)
用半加器搭建全加器 使用Verilog语言
Using a half adder to build a full adder, using the Verilog language (2017-09-18, Verilog, 274KB, 下载1次)