32位MIPS处理器的流水线设计
Pipelined Design of 32 bit MIPS Processor (2024-02-19, Verilog, 0KB, 下载0次)
此存储库包含32位up-down计数器的源代码和文档。计数器在Verilog中实现，并在Intel Quarter Prime中设计。
This repository contains the source code and documentation for a 32-bit up-down counter. The counter is implemented in Verilog and is designed in Intel Quarter Prime. (2024-01-27, Verilog, 0KB, 下载0次)
powerpc处理器原型和半导体初创企业计划示例，
powerpc processor prototype and an example of semiconductor startup biz plan, (2019-02-02, Verilog, 0KB, 下载0次)
在Verilog.中实现MIPS-ISA的超标量处理器。，
An implementation of super scalar processor for MIPS ISA in Verilog., (2020-06-09, Verilog, 0KB, 下载0次)
具有中断和预测器的五级流水线mips cpu，
Five-stage pipeline mips cpu with interrupts and predictor, (2017-03-08, Verilog, 0KB, 下载0次)
MIPS汇编计算机处理器设计（2位和8位），
MIPS Assembly computer processor designs (2- & 8-bit), (2019-04-13, Verilog, 0KB, 下载0次)
一种在一个周期内执行指令的mips处理器。，
A mips processor that executes instructions in one cycle., (2019-06-18, Verilog, 0KB, 下载0次)
基于32位MIPS的处理器，包括45条指令。，
processor based in 32-bit MIPS , including 45 instructions., (2017-07-20, Verilog, 0KB, 下载0次)
硬件设计的最终项目-在Verilog.中设计MIPS处理器。，
Final project for Hardware Design - designing a MIPS processor in Verilog., (2020-12-18, Verilog, 0KB, 下载0次)
基于 MIPS CPU的银行排队器的汇编代码实现,
MIPS CPU based assembly code implementation of bank queueer, (2022-06-16, Verilog, 0KB, 下载0次)
MIPS单周期处理器的Verilog实现，
A Verilog implementation of a MIPS single cycle processor, (2019-09-12, Verilog, 0KB, 下载0次)
使用Verilog构建的MIPS处理器的简化版本，
A simplified version of the MIPS processor built using Verilog, (2013-12-18, Verilog, 0KB, 下载0次)
32位MIPS处理器的Verilog说明，
Verilog Description for a 32bit MIPS Processor, (2018-02-10, Verilog, 0KB, 下载0次)
一种32位微处理器，具有42条指令（包括乘法和除法）、8 X 32寄存器和2048 X 32 Ram，具有共享...，
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly. (2022-02-19, Verilog, 0KB, 下载0次)
Verilog中的单周期和5级流水线MIPS模拟器，
Single Cycle & 5-stage Pipelined MIPS Simulator in Verilog, (2020-07-08, Verilog, 0KB, 下载0次)
Verilog HDL中的32位MIPS处理器实现，
A 32-bit MIPS Processor Implementation in Verilog HDL, (2022-05-18, Verilog, 0KB, 下载0次)
MyProc是一个用verilog实现的处理器，用于教育目的。，
MyProc is a processor implemented in verilog for educational purposes., (2017-07-22, Verilog, 0KB, 下载0次)
基于FPGA搭建的ADS芯片的SPI通信接口
内主要含SPI协议，指令译码控制器，及控制信号寄存器堆
SPI communication interface of ads chip based on FPGA
It mainly contains SPI protocol, instruction decoding controller and control signal register stack (2020-07-07, Verilog, 3541KB, 下载21次)
可以直接在quatus开发环境中打开工程文件，ISE或VAVADO中需要重新选择IP核和添加源文件即可建立工程，可以采用MODELSIM仿真，滤波器参数可以在MATLAB中根据需要修改，文件中提供了滤波器设计函数。
msk demod, verilog language develop (2020-04-25, Verilog, 7422KB, 下载0次)
通过4位加法器实现32位加法器，使用串行进位的方式首先设计一个8位全加器，然后在8位全加器的基础上设计实现32位全加器
A 32 bit adder is implemented through a 4 bit adder. First, a 8 bit full adder is designed using serial carry. Then, a 32 bit full adder is designed on the basis of 8 bit full adder. (2018-03-18, Verilog, 530KB, 下载3次)