这个名为“计数器”的Verilog模块实现了一个具有宽度参数（width）的可配置计数器。
This Verilog module named "counter" implements a configurable counter with a width parameter (WIDTH). (2024-04-04, Verilog, 0KB, 下载0次)
在Verilog中设计处理器
Designing a Processor in Verilog (2024-02-28, Verilog, 0KB, 下载0次)
D触发器Verilog
D Flip Flop Verilog (2024-01-13, Verilog, 0KB, 下载0次)
verilog阶乘计算器
verilog Factorial Calculator (2023-12-23, Verilog, 0KB, 下载0次)
在Xilinx FPGA中使用Verilog为远程汽车控制器创建了自己的红外线发射器，
Created my own infra-red transmitter for a remote car controller using Verilog in Xilinx FPGA, (2023-08-16, Verilog, 0KB, 下载0次)
这是关于使用Verilog VHDL实现（2,1,4）卷积编码器和维特比解码器。
This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL. (2020-08-12, Verilog, 6KB, 下载4次)
它是用于sdd1306显示器的i2c主控帧缓冲器的fpga实现
It is a fpga implementation of an i2c master, framebuffer for sdd1306 display (2021-05-14, Verilog, 17KB, 下载0次)
露天矿ac97控制器verilog核心
opencores ac97 controller verilog core (2016-04-09, Verilog, 119KB, 下载0次)
Mips管道处理器
Mips Pipeline Processor (2018-10-16, Verilog, 18KB, 下载0次)
简单sdram控制器
simple sdram controller (2021-02-09, Verilog, 6168KB, 下载0次)
CyNAPSE神经形态加速器：以完全可合成的形式编写的数字Spiking神经网络加速器...
The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL (2019-09-25, Verilog, 551KB, 下载0次)
一些用Modelsim仿真的verilog源代码，包括计数器，移位寄存器等。
Some Verilog source codes simulated by Modelsim include counter, shift register, etc. (2020-04-14, Verilog, 2412KB, 下载1次)
可以实现存储数据并读取的简单功能，适用于初级学者，
D触发器简单实现
You can implement the simple function of storing data and reading it (2020-03-13, Verilog, 1KB, 下载0次)
精简指令集cpu实现,包括时钟产生，累加器，指令寄存器等主要模块，以及主状态机的实现
Reduced instruction set cpu implementation, including clock generation, accumulator, instruction register and other main modules, as well as the implementation of the main state machine (2019-04-19, Verilog, 90KB, 下载1次)
本代码为verilog语言编写的按键计数器代码，适用于FPGA小脚丫开发版
Key counter of Beijing University of Posts and Telecommunications (2018-11-30, Verilog, 13KB, 下载3次)
温度传感器ds18b20的温度通过lcd1620和数码管显示
The temperature of the temperature sensor DS18B20 is displayed by lcd1620 and digital tube. (2018-07-18, Verilog, 1434KB, 下载3次)
一位十进制数码管计数的实验，本次实验利用了三个程序，一个是计数器，一个是分频器，一个是数码管显示。随着时钟的上升沿和下降沿计数器完成计数时，加入一个分频器，可以改变时钟的频率，让0-9的计数可以不会因为频率太快而能在开发板上显示。
A decimal digit tube counting experiment, this experiment has used three procedures, one is the counter, one is the frequency divider, and the other is the digital tube display. With the counting of the clock rising and falling along the counter, adding a frequency divider can change the frequency of the clock, so that the count of 0-9 can be displayed on the development board without being too fast. (2018-05-24, Verilog, 15KB, 下载2次)
实现一个简易的计算器功能，适用于新手借鉴学习下
To achieve a simple calculator function, suitable for beginners learn from learning. (2018-05-18, Verilog, 1203KB, 下载3次)
通用计数器程序，便于初学者掌握verilog HDL语言的进行计数器设计原则
General counter program is easy for beginners to master the counter design principles of Verilog HDL language. (2018-04-18, Verilog, 4109KB, 下载1次)
用verilog语言设计了一个分频器，晶振频率为50MHz
A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz (2017-11-14, Verilog, 4146KB, 下载5次)