定制16位处理器设计：微体系结构、RTL和UVM验证。
Custom 16-bit processor design: microarchitecture, RTL, and UVM verification. (2023-12-23, Verilog, 0KB, 下载0次)
在Xilinx FPGA上测试了Verilog中MIPS处理器的实现。
An implementation of MIPS processor in Verilog, tested on a Xilinx FPGA. (2023-12-17, Verilog, 0KB, 下载0次)
Verilog HDL中编码的非常精简的指令集处理器，
very-reduced-instruction-set processor coded in the Verilog HDL, (2023-07-17, Verilog, 0KB, 下载0次)
Verilog中的32位FPU（加法器-减法器-乘法器），
A 32-bit FPU (Adder Subtracter Multiplier) in Verilog, (2022-12-22, Verilog, 0KB, 下载0次)
使用Verilog实现MIPS处理器的第三个计算机工程项目，
3rd Computer Engineering project of MIPS processor implementation using Verilog, (2019-11-29, Verilog, 0KB, 下载0次)
计算机架构项目（2015年春季）：Verilog中基于MIPS的处理器，
Computer Architecture Project (Spring 2015): MIPS -Based Processor in Verilog, (2015-12-05, Verilog, 0KB, 下载0次)
基于 MIPS 指令集子集的单周期处理器设计,
Single cycle processor design based on MIPS instruction set subset, (2022-06-21, Verilog, 0KB, 下载0次)
基于Verilog设计MIPS处理器并在De2i-150 FPGA板上综合，
Design MIPS processor based on Verilog and synthesize on De2i-150 FPGA board, (2019-07-05, Verilog, 0KB, 下载0次)
用Verilog.编写的简单的5级流水线MIPS风格处理器。，
A simple, 5 stage pipelined, MIPS style processor written in Verilog., (2022-05-29, Verilog, 0KB, 下载0次)
使用Vivado实现MIPS单周期流水线处理器，
Use Vivado to implement MIPS single-cycle and pipeline processor, (2019-09-20, Verilog, 0KB, 下载0次)
实现了32位2级流水线MIPS指令处理器，
Implemented a 32 bit, 2 stage Pipelined MIPS Instruction Processor, (2021-12-02, Verilog, 0KB, 下载0次)
实现了基于RISC的28条指令8位MIPS处理器。，
Implemented RISC-based 28 instructions 8 bit MIPS processor., (2020-07-08, Verilog, 0KB, 下载0次)
在Verilog HDL中完成的Mips处理器的多周期硬件描述，
The Multi-Cycle hardware description of Mips processor done in Verilog HDL, (2022-12-18, Verilog, 0KB, 下载0次)
使用UVM的MIPS处理器的模拟和功能验证。，
Simulation and functional verification of a MIPS processor using UVM., (2019-09-09, Verilog, 0KB, 下载0次)
Verilog HDL中的32位MIPS处理器实现，
A 32-bit MIPS Processor Implementation in Verilog HDL, (2022-12-18, Verilog, 0KB, 下载0次)
流水线RISC处理器（类似于MIPS）的设计和Verilog实现。，
Design and a Verilog implementation of a pipelined RISC processor (similar to MIPS )., (2022-05-08, Verilog, 0KB, 下载0次)
用于修改精简MIPS32指令集的简单单周期处理器。，
Simple single cycle processor for modified reduced MIPS32 instruction set., (2019-11-30, Verilog, 0KB, 下载0次)
通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器,
By learning Write CPU by Yourself, the processor compatible with MIPS32 instruction set architecture OpenMIPS (five level pipeline structure) implemented in the book is simplified into a single instruction cycle processor, (2022-03-02, Verilog, 0KB, 下载0次)
可综合I2C+FPGA控制+移位寄存器。用于芯片内部控制信号读入读出。
Integrated I2C + FPGA control + shift register (2021-04-26, Verilog, 13KB, 下载0次)
利用FPGA驱动AD8285进行寄存器配置
Drive AD8285 for configuration (2019-06-05, Verilog, 813KB, 下载26次)