具有模式选择的BCD计数器、BCD下降计数器和BCD上升下降计数器的RTL设计使用Verilog文件操作将输出存储在文本文件中。
RTL design for a BCD Counter, bcd down counter and bcd updown counter with mode select store the output in a text file using Verilog file operations. (2024-03-11, Verilog, 0KB, 下载0次)
多路复用器2x1-Verilog SystemVerilog
Multiplexador 2x1 - Verilog SystemVerilog (2024-02-22, Verilog, 0KB, 下载0次)
单周期risc-v处理器的RTL代码是用verilog编写的。Alu、Alu控制、控制单元、数据存储器、指令存储器、指令获取、指令处理、寄存器文件、符号扩展和顶层模块用verilog编写。
RTL code of single cycle risc-v procesor is written in verilog. Alu, Alu control, control unit, data memory, instruction memory, instruction fetch, instruction processing, register file, sign extension, and top level modules are written in verilog. (2024-02-12, Verilog, 0KB, 下载0次)
FPGA数字示波器
FPGA Digital Oscilloscope (2024-01-05, Verilog, 0KB, 下载0次)
Arty FPGA板启动器项目
Arty FPGA board starter project (2022-09-13, Verilog, 14KB, 下载0次)
CNN频域加速器
CNN Accelerator in Frequency Domain (2020-02-22, Verilog, 9033KB, 下载0次)
同步器的类型
Types of Synchronizer (2023-02-20, Verilog, 781KB, 下载0次)
二进制计数器MOJO-V3-VHDL，，
Binary-counter-MOJO-V3-VHDL,, (2018-06-20, Verilog, 22KB, 下载0次)
LC3处理器的Verilog实现
Verilog implementation of the LC3 processor (2013-08-12, Verilog, 8KB, 下载0次)
低功率乘法器累加器
Low Power Multiplier Accumulator (2016-10-21, Verilog, 3KB, 下载0次)
Verilog超标量MIPS处理器
Verilog superscalar MIPS processor (2015-12-15, Verilog, 947KB, 下载0次)
verilog中的简单sram控制器。
Simple sram controller in verilog. (2016-06-05, Verilog, 12KB, 下载0次)
DVI至LVDS Verilog转换器
DVI to LVDS Verilog converter (2016-09-03, Verilog, 187KB, 下载0次)
使用FF锁存单元的基于单元库的标准存储器编译器
Standard Cell Library based Memory Compiler using FF Latch cells (2023-05-26, Verilog, 4994KB, 下载0次)
Verilog SDRAM内存控制器
Verilog SDRAM memory controller (2017-05-13, Verilog, 445KB, 下载0次)
SDIO 接口，实现SD卡的控制器功能，带有详细的注释
SDIO Interface,to realize the controller of SD Card,and have detail description. (2019-08-14, Verilog, 5KB, 下载34次)
FX3作为FPGA核心的Slave完成与PC的通信验证例程。其中引脚需要按照自己的FX3开发板进行配置。默认配置是HSC的ALTERA开发板，EP4CE22F17C8+CYUSB3014。
同步FIFO传输，使用CyConsole验证通过。内附SignalTapII观察波形。
FX3, as the core of the FPGA Slave, completes the communication validation routines with PC. The pins need to be configured according to their own FX3 development board. The default configuration is HSC's ALTERA development board, EP4CE22F17C8+CYUSB3014.Synchronous FIFO transmission is verified by CyConsole. SignalTapII waveform is attached. (2018-11-14, Verilog, 11337KB, 下载9次)
简易加密器及解密器设计，3重加密解密环节，采用异位，与密匙运算，对字母数据额外加密等加密方法
Simple encryption and decryption device design, 3 encryption and decryption links, the use of ectopic and key operations, the encryption of alphabet data and other encryption methods. (2018-07-19, Verilog, 1KB, 下载2次)
调试bcm5396，写入和读取内部寄存器功能。功能验证可以用
Debug bcm5396, write and read the internal register function. Functional validation can be used (2017-12-24, Verilog, 2KB, 下载21次)
设计一个100人投票器，超过70人算通过，用verilog语言设计
Design a 100 person voter, more than 70 people passed, using Verilog language design (2017-11-14, Verilog, 16761KB, 下载3次)