2023 夏季学期《数字逻辑与处理器基础实验》课程大作业
Major assignment of Digital Logic and Processor Basic Experiment in 2023 summer semester (2024-03-22, Verilog, 0KB, 下载0次)
16位MIPS微处理器在ICC上的实现
implementation of 16 BITS MIPS MICROPROCESSOR on ICC (2024-03-03, Verilog, 0KB, 下载0次)
单周期MIPS处理器在Nexys4 DDR上的实现
Implementation of Single Cycle MIPS Processor on Nexys4 DDR (2023-12-27, Verilog, 0KB, 下载0次)
具有MIPS风格指令集的32位计算机处理器。，
A 32-bit Computer processor with a MIPS-esque instruction set., (2023-08-29, Verilog, 0KB, 下载0次)
具有内置L1缓存的5级流水线MIPS处理器的Verilog行为建模。，
Verilog behavioral modeling of a 5-stage pipeline MIPS processor with builtin L1 cache., (2016-01-07, Verilog, 0KB, 下载0次)
该项目是基于5级流水线MIPS处理器的实现。，
This project is an implementation of a 5-stage pipelined MIPS based processor., (2022-12-20, Verilog, 0KB, 下载0次)
在Verilog中模拟的具有MIPS指令集架构的多周期处理器，
A multicycle processor with MIPS instruction set architecture simulated in Verilog, (2022-09-16, Verilog, 0KB, 下载0次)
使用MIPS指令集架构在Verilog中模拟的单周期处理器。，
A single cycle processor simulated in Verilog using MIPS instruction set architecture., (2022-09-16, Verilog, 0KB, 下载0次)
5级MIPS流水线处理器：仅限I型和R型指令，
5 Stage MIPS Pipelined Processor: I-type and R-type instructions only, (2019-05-03, Verilog, 0KB, 下载0次)
Rowan U.的定制16位MIPS处理器（无流水线），2018年夏季，
Customized 16-bit MIPS processor (no pipelining) for Rowan U., Summer 2018, (2018-06-28, Verilog, 0KB, 下载0次)
用于MIPS32 Release 1的五级管道处理器。频率>120MHz。，
A five stage pipeline processor for MIPS32 Release 1. Frequency > 120MHz., (2019-09-20, Verilog, 0KB, 下载0次)
具有危险检测和转发单元的MIPS处理器的流水线实现。，
A pipelined implementation of the MIPS processor featuring hazard detection and Forwarding Unit., (2022-01-24, Verilog, 0KB, 下载0次)
具有5级管道的32位MIPS处理器，
32-bits MIPS Processor with 5-stage pipeline, (2021-05-16, Verilog, 0KB, 下载0次)
用Verilog编写的5级流水线32位MIPS微处理器，
5-stage pipelined 32-bit MIPS microprocessor written in Verilog, (2022-07-21, Verilog, 0KB, 下载0次)
MIPS-32单周期处理器，具有R型指令。通过Verilog.编程。，
MIPS -32 single cycle processor with R type instruction. Programmed via Verilog., (2019-02-16, Verilog, 0KB, 下载0次)
Verilog HDL.中的MIPS处理器（单周期、多周期、流水线）实现。，
MIPS Processor (Single-Cycle, Multi-Cycle, Pipeline) Implementation in Verilog HDL., (2021-02-05, Verilog, 0KB, 下载0次)
具有写回缓存和检查点回滚硬件支持的Tiger MIPS处理器，
Tiger MIPS processor with write-back cache and checkpoint roll-back hardware support, (2018-02-18, Verilog, 0KB, 下载0次)
在Verilog中设计MIPS CPU；在此RISC内核中运行AES编码器；，
Design a MIPS CPU in Verilog; Run AES encoder in this RISC-core;, (2015-12-05, Verilog, 0KB, 下载0次)
具有侦听MSI和管道总线的2核MIPS R10K OoO处理器，
2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus, (2018-01-05, Verilog, 0KB, 下载0次)
32位MIPS处理器，旨在符合MIPS32 Release 1 ISA。，
A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA., (2015-07-29, Verilog, 0KB, 下载0次)