Verilog中的RISC-V处理器
RISC-V processor in Verilog (2024-01-07, Verilog, 0KB, 下载0次)
Ambiente Verilog每个处理器都是didattico sEP8
Ambiente Verilog per processore didattico sEP8 (2023-11-23, Verilog, 0KB, 下载0次)
用于数字通信的块交织器。（Verilog）
Block interleaver for digital communication.（Verilog） (2023-11-08, Verilog, 0KB, 下载0次)
使用verilog实现寄存器文件
Implementation of a register file using verilog (2023-11-10, Verilog, 0KB, 下载0次)
Verilog有限脉冲响应滤波器，
Verilog finite impulse response filter, (2023-09-14, Verilog, 0KB, 下载0次)
流水线CORDIC处理器SystemVerilog，，
Pipelined CORDIC Processor SystemVerilog,, (2014-01-08, Verilog, 0KB, 下载0次)
Verilog SPI RAM控制器，
Verilog SPI RAM controller, (2023-07-24, Verilog, 0KB, 下载0次)
基于FPGA的中值滤波器
FPGA-based Median Filter (2014-07-17, Verilog, 460KB, 下载0次)
JPEG解码器的Verilog代码
Verilog Code for a JPEG Decoder (2018-03-07, Verilog, 160KB, 下载1次)
基于Verilog的BCH编解码器
Verilog based BCH encoder decoder (2022-09-26, Verilog, 62KB, 下载1次)
verilog rs232串口收发控制器
verilog rs232 control (2021-03-12, Verilog, 4KB, 下载0次)
现有16位寄存器。初始值为0。每个时钟周期寄存器的值会左移1位，并且将输入的数据data_in作为寄存器的最低位，寄存器原来的最高位将被丢弃。要求每个周期实时输出该16位寄存器对7求余的余数data_out[20]。
Existing 16 bit register. The initial value is 0. The value of each clock cycle register will shift 1 bit to the left, and the input data will be_ In as the lowest bit of the register, the original highest bit of the register will be discarded. It is required to output the remainder data of the 16 bit register to 7 in real-time in each cycle_ out[20]. (2020-05-16, Verilog, 447KB, 下载1次)
数电实验FPGA verilog代码，包括秒表、全加器、半加器等。
FPGA Verilog code for digital experiment (2020-04-29, Verilog, 8KB, 下载1次)
分数倍内插滤波器相关论文，经供参考，（为获取下载资格）
For reference, papers on fractional interpolation filters (for download qualification) (2019-07-10, Verilog, 1198KB, 下载1次)
CANip控制器FPGA代码实现CAN控制器功能
Realization of CAN Controller Function by FPGA Code of CANip Controller (2018-12-19, Verilog, 18KB, 下载10次)
verilog实现3-8译码器改全加器，硬件为小脚丫MAX10M02SCM153
Verilog implements 3-8 decoder to full adder. The hardware is small foot MAX10M02SCM153. (2018-11-29, Verilog, 4439KB, 下载0次)
FIR滤波器电路主要包括两个主要的功能模块，移位寄存器组模块，用于存储串行进入滤波器的数据，乘法器模块，用于进行FIR计算。本设计主要负责存储8个八位宽输入数据信号，将其作为计算模块的输入。
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FIR filter circuit mainly includes two main functional modules, shift register group module, used to store the serial access filter data, multiplier module, used for FIR calculation. This design is mainly responsible for storing 8 eight bit wide input data signals as input to the calculation module. (2018-08-22, Verilog, 16KB, 下载4次)
此功能为altera fpga 的sdram 控制器，串口接收与发送
This feature altera fpga sdram controller, serial port to receive and send (2017-12-10, Verilog, 1178KB, 下载8次)
《四则运算小计算器设计过程实录》day1
verilog HDL code for day1,7 .rar documents in total.For more code u can put ur eye on my account. (2017-07-21, Verilog, 2KB, 下载6次)
IR传感器使用Verilog语言编程，平台实在FPGA Cycle 4上实现
IR sensor using Verilog programming language, the platform is really FPGA Cycle 4 implementation (2017-07-15, Verilog, 9827KB, 下载2次)