目前使用MIPS架构制作了一个ALU，但不久将制作一个完整的处理器。，
Currently made an ALU using MIPS architecture, but will make a full processor soon., (2023-10-19, Verilog, 0KB, 下载0次)
具有侦听MSI和管道总线的2核MIPS R10K型OoO处理器，
2-core MIPS R10K style OoO Processor with Snooping MSI and Pipeline Bus, (2019-01-19, Verilog, 0KB, 下载0次)
MIPS数据存储器回写（MEM WB）实现，包括Verilog、MIPS和Testbench，
MIPS Data Memory Write Back (MEM WB) implementation including Verilog, MIPS and Testbench, (2019-12-14, Verilog, 0KB, 下载0次)
计算机体系结构-使用自主开发的ISA在verilog中进行MIPS处理器模拟，
Computer Architecture- MIPS Processor simulation in verilog with self developed ISA, (2019-08-25, Verilog, 0KB, 下载0次)
Verilog HDL.中单周期MIPS处理器的BAM（二进制角度调制）模块。，
BAM (Binary angle modulation) module for a single-cycle MIPS processor in Verilog HDL., (2019-02-04, Verilog, 0KB, 下载0次)
课程项目：实现32位MIPS流水线处理器设计并应用于FGPA，
Course Project: Realized 32-bit MIPS pipeline processor design and applied it on FGPA, (2020-02-17, Verilog, 0KB, 下载0次)
模拟MIPS格式的处理器，用Verilog编码，内置Quartus Prime Lite 16.1，
Processor mimicking MIPS format, coded in Verilog and built in Quartus Prime Lite 16.1, (2018-09-27, Verilog, 0KB, 下载0次)
CS2201-计算机体系结构课程的32位MIPS RISC处理器最终项目，
32 bits MIPS RISC Processor final project for the course CS2201 - Computer Architecture, (2019-07-06, Verilog, 0KB, 下载0次)
具有5级管道、缓存、分支预测器、TLB、UNIX OS SoC.、。，
A Dual-issue MIPS CPU core feature with 5-level-pipeline, cache, Branch Predictor, TLB, UNIX OS SoC., (2021-06-29, Verilog, 0KB, 下载0次)
使用DE10 Lite FPGA开发板的32位5级流水线MIPS处理器，
32-bit, 5-stage pipelined MIPS processor using DE10-Lite FPGA development board, (2020-08-27, Verilog, 0KB, 下载0次)
CPU用于5级管道，并尝试添加MMU、缓存、分支预测器等，
CPU for 5-stage pipeline, and trying to add MMU, Cache, branch predictor and etc, (2020-07-18, Verilog, 0KB, 下载0次)
Verilog HDL实现的5级流水线MIPS处理器（包括旁路和暂停），
5-stage Pipelined MIPS Processor Implemented by Verilog HDL(Include Bypass and Stall), (2019-10-08, Verilog, 0KB, 下载0次)
在Verilog和Intel Max 10 FPGA系列上的MIPS微处理器的基本实现。，
Basic implementation of a MIPS microprocessor on Verilog and Intel Max 10 FPGA family., (2019-11-25, Verilog, 0KB, 下载0次)
一种基本微处理器，无互锁管道级，能够使用基于向量的指令。，
A basic microprocessor without interlocked Pipeline stages that is capable of using vector based instructions., (2019-09-25, Verilog, 0KB, 下载0次)
Verilog HDL中的16位MIPS处理器实现，
A 16-bit MIPS Processor Implementation in Verilog HDL, (2020-08-30, Verilog, 0KB, 下载0次)
在Verilog中实现的简单5级单流水线MIPS处理器。（正在进行的工作），
A simple 5-stage single-pipeline MIPS processor implemented in Verilog. (WORK IN PROGRESS), (2018-03-26, Verilog, 0KB, 下载0次)
实现Verilog代码来模拟MIPS处理器，并使用Python GUI汇编程序。，
Implement a Verilog code to simulate the MIPS Processor and using Python GUI assembler., (2017-12-23, Verilog, 0KB, 下载0次)
用bufif0和bufif1设计一个2选一选择器的延迟模块
Model Delay of a Mux2-1 using bufif0 and bufif1 in
Verilog HDL Digital System Design (2020-04-25, Verilog, 11KB, 下载1次)
一个简易的数字示波器，适合初学者学习。希望你能学到知识。
A simple digital oscilloscope, suitable for beginners.I hope you can learn knowledge. (2018-07-13, Verilog, 4035KB, 下载0次)
1. 本设计以1Hz的时钟作为基准信号，测量10Hz~10MHz的频率。
2. 脉冲信号的频率就是在1Hz内所产生的脉冲个数，因此1S内计数器所记录的结果，就是被测信号的频率。
3. 在电路中，采用8个级联的模10计数器进行计数，8个模10计数器分别输出第1位至第8位的8421BCD码。
4. 简易频率计由三个模块组成，分别是控制模块，模10计数器模块以及锁存器模块。
1. the design uses the 1Hz clock as the reference signal to measure the frequency of 10Hz~10MHz.
2. the frequency of the pulse signal is the number of pulses generated in 1Hz, so the result of the counter recorded in 1S is the frequency of the measured signal.
3. in the circuit, 8 cascaded mode 10 counters are used to count, and 8 mode 10 counters output first bit to eighth bit 8421BCD codes respectively.
4. the simple frequency meter consists of three modules: control module, module 10 counter module and latch module. (2018-06-21, Verilog, 3498KB, 下载1次)