ADRV9009 zc706上的不透明语音接收器。使用MATLAB 2023a、Vivado 2022.2、Simulink和HDL编码器。HDL编码器源代码输出是工作产品，是开源设计。
Opulent voice receiver on the ADRV9009 zc706. Uses MATLAB 2023a, Vivado 2022.2, Simulink, and HDL Coder. The HDL Coder source code output is the work product, and is an open source design. (2024-03-11, Verilog, 0KB, 下载0次)
序列检测器的Verilog代码
Verilog code for a Sequence detector (2024-01-14, Verilog, 0KB, 下载0次)
Verilog Morse代码转换器
Verilog Morse Code Translator (2023-12-19, Verilog, 0KB, 下载0次)
用于模拟神经网络加速器中芯片内数据流的片上网络（NoC）模拟器
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator (2023-11-10, Verilog, 0KB, 下载0次)
FPGA的一系列加速器，
A bunch of accelerators for FPGAs, (2023-10-25, Verilog, 0KB, 下载0次)
MOS 6502微处理器的Verilog实现，
Verilog implementation of MOS 6502 microprocessor, (2023-10-03, Verilog, 0KB, 下载0次)
该Repo包含使用Verilog HDL的基本逻辑块（例如计数器、多路复用器......等）的RTL代码。，
This Repo contains RTL codes for basic logic blocks (eg. Counter, mux ... etc.), using Verilog HDL. (2023-09-29, Verilog, 0KB, 下载0次)
ARM处理器的实现，
An implementation of ARM processor, (2023-09-19, Verilog, 0KB, 下载0次)
带FPGA硬件的PID控制器
PID controller with FPGA hardware (2019-10-05, Verilog, 102KB, 下载0次)
Verilog中的FIR滤波器
FIR Filter in Verilog (2019-11-17, Verilog, 422KB, 下载0次)
处理器缓存的Verilog实现。
A Verilog implementation of a processor cache. (2017-12-29, Verilog, 333KB, 下载0次)
1949年EDSAC计算机的FPGA Verilog实现，带有动画磁带读取器、面板、电传打印机和CRT示波器
FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope (2021-02-22, Verilog, 3598KB, 下载0次)
MIT CADR原始版本和模拟器
MIT CADR original verilog and simulator (2016-01-02, Verilog, 52816KB, 下载0次)
Verilog中Sobel滤波器的实现
Implementation of Sobel Filter in Verilog (2017-03-10, Verilog, 57KB, 下载0次)
分数倍内插滤波器相关论文，经供参考，（为获取下载资格）
For reference, papers on fractional interpolation filters (for download qualification) (2019-07-10, Verilog, 1198KB, 下载1次)
AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明
AD7760 Full Function Support with Additional Instructions (2018-12-21, Verilog, 35202KB, 下载42次)
CANip控制器FPGA代码实现CAN控制器功能
Realization of CAN Controller Function by FPGA Code of CANip Controller (2018-12-19, Verilog, 18KB, 下载10次)
verilog实现3-8译码器改全加器，硬件为小脚丫MAX10M02SCM153
Verilog implements 3-8 decoder to full adder. The hardware is small foot MAX10M02SCM153. (2018-11-29, Verilog, 4439KB, 下载0次)
flash接口控制器的VHDL以及verilog源代码和Testbench
Flash interface controller VHDL and Verilog source code and Testbench (2018-06-08, Verilog, 17KB, 下载8次)
《四则运算小计算器设计过程实录》day1
verilog HDL code for day1,7 .rar documents in total.For more code u can put ur eye on my account. (2017-07-21, Verilog, 2KB, 下载6次)