设计32位基本处理器单元，对指令进行解码，并执行ALU的不同操作。，
Design of 32-bit basic processor unit which decodes the instruction and performs different operations of ALU., (2023-08-27, Verilog, 0KB, 下载0次)
我们设计了一个基于MIPS架构的5级流水线处理器，
We have designed a 5 Stage Pipeline Processor based on the MIPS architecture, (2020-06-09, Verilog, 0KB, 下载0次)
使用Verilog HDL开发的MIPS处理器，请阅读README.md文件以了解详细说明，
Developed MIPS Processor Using Verilog HDL, Please Read README.md File for Detailed Description, (2019-12-14, Verilog, 0KB, 下载0次)
Verilog-SystemVerilog中的全流水线MIPS CPU，具有高级分支预测、寄存器重命名和值预测，
Fully pipelined MIPS CPU in Verilog SystemVerilog with advanced branch prediction, register renaming, and value prediction, (2016-02-21, Verilog, 0KB, 下载0次)
这是一个基于MIPS的处理器，我在毕业时做了计算机架构和组织实验室，
This is a MIPS based processor developed while I made the Architecture and Organization of Computers Laboratory in graduation, (2022-02-28, Verilog, 0KB, 下载0次)
用HDL语言实现MIPS处理器，并在Synopsys Design Compiler和中进行优化，
Implementing MIPS processor with HDL language and optimization in Synopsys Design Compiler and, (2021-10-06, Verilog, 0KB, 下载0次)
此存储库包含Verilog.中32位单周期MIPS处理器的以下指令的实现。，
This repository contains implementation of the following instructions for 32-bit Single Cycle MIPS processor in Verilog., (2018-12-01, Verilog, 0KB, 下载0次)
基于MIPS处理器作为硬件的数字设计的学术项目，使用verilog作为硬件描述语言，
Academic Project based on digital design of MIPS processor as a hardware using verilog as a hardware description language, (2019-10-09, Verilog, 0KB, 下载0次)
实现MIPS指令集体系结构的子集的处理器，用Verilog为Altera FPGA编写，
A processor which implements a subset of the MIPS Instruction Set Architecture, written in Verilog for an Altera FPGA, (2018-12-22, Verilog, 0KB, 下载0次)
德黑兰大学计算机体系结构课程的项目MIPS处理器的多周期实现，
Multi Cycle Implementation of MIPS processor, a project for Computer Architecture course in University of Tehran, (2021-02-13, Verilog, 0KB, 下载0次)
使用Verilog的流水线RISC架构MIPS处理器。具有转发、暂停和分支控制危险单元（次要...，
Pipelined RISC Architecture MIPS Processor using Verilog. Full pipelined with forwarding, stalling, and branch control hazard unit (minor errors with race conditions and sw forwarding, no jump). Spring 17. (2018-11-15, Verilog, 0KB, 下载0次)
三个数据路径概念的实现：单周期、多周期和流水线。处理器与“Computer Orga...，
Implementation of the three datapath concepts: singlecycle, multicycle and pipeline. Processors were implemented alongside "Computer Organisation and Design" lecture of TU Berlin. Processor designs are based on book contents of "Computer Organisation and Design" by D. Patterson and J. Hennessy (2018-07-08, Verilog, 0KB, 下载0次)
我们创建了一个多核处理器，旨在并行化程序执行并允许优化计算单元。，
We created a multicore processor with the intent of parallelizing program execution and allowing for optimized computing units., (2020-12-15, Verilog, 0KB, 下载0次)
在Verilog中实现的16位MIPS处理器（作为计算机组织课程的一部分），
16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course), (2019-12-30, Verilog, 0KB, 下载0次)
MIPS32处理器 - 清华大学计算机组成原理课程与软件工程课程挑战性联合实验项目,
MIPS32 Processor Tsinghua University Computer Composition Principle Course and Software Engineering Course Challenge Joint Experiment Project, (2020-07-07, Verilog, 0KB, 下载0次)
一种具有分支预测和CP1（FPU）支持的轻量级可合成9级流水线MIPS处理器。，
A light-weighted synthesizable 9-stage-pipelined MIPS processor with branch prediction and CP1(FPU) support., (2022-09-15, Verilog, 0KB, 下载0次)
在Verilog中为CS 4341-数字逻辑和计算机设计实现的32位MIPS处理器。，
32-Bit MIPS processor implemented in Verilog for CS 4341 - Digital Logic and Computer Design., (2016-05-01, Verilog, 0KB, 下载0次)
使用Verilog HDL开发支持 MIPS -C3指令集(共50条指令)的 MIPS 流水线处理器,
Use Verilog HDL to develop MIPS pipeline processors that support MIPS - C3 instruction sets (50 instructions in total), (2019-07-14, Verilog, 0KB, 下载0次)
在MIPS体系结构下包含CPU、操作系统和编译器的计算机系统。，
A computer system containing CPU, OS and Compiler under MIPS architecture., (2021-09-09, Verilog, 0KB, 下载0次)
本表决器包括LED外设、按键外设、及数码管外设，按键用于三人分别进行选择，LED用于指示各人的选择情况，数码管用于记录选择人数。
The voting device includes LED peripherals, key peripherals, and nixie tube peripherals. The buttons are used for three people to select respectively. The LED is used to indicate each person's choice, and the nixie tube is used to record the number of people selected. (2020-07-03, Verilog, 209KB, 下载0次)