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按分类查找All VHDL/FPGA/Verilog(362) 
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[VHDL/FPGA/Verilog] MPSoC-FPGA-HIL-Platform

本论文的主题是基于FPGA的半实物仿真源代码库的无人驾驶汽车自动驾驶系统传感器故障注入芯片级测试平台。
The thesis topic is A Chip-level Testing Platform for Sensor Fault Injection of Unmanned Vehicles Autopilot System with FPGA-based Hardware-in-the-loop Simulation source code repository. (2024-02-10, matlab, 0KB, 下载1次)

http://www.pudn.com/Download/item/id/1707552676837820.html

[VHDL/FPGA/Verilog] ightweight-and-Real-Time-Infrared-Image-Processor

这是“基于FPGA的轻量级实时红外图像处理器”论文的附加代码(Xilinx Verilog HDL项目和Matlab)。请注意,仅发布了整个设计的一部分。为保护商业秘密,保留其他代码。
This is the attach codes (Xilinx Verilog HDL Project and Matlab) for the paper "Lightweight and Real-Time Infrared Image Processor Based on FPGA". Note that only a part of the whole design is released. The other codes are reserved due to the protection of trade secrets. (2024-02-06, matlab, 0KB, 下载1次)

http://www.pudn.com/Download/item/id/1707208157500132.html

[VHDL/FPGA/Verilog] 基于MATLAB模型设计的FPGA开发与实现

MATLAB的SIMULINK和FPGA联合设计滤波器等,摆脱了传统的代码设计。
MATLAB's SIMULINK and FPGA jointly design filters and so on, and get rid of the traditional code design. (2018-05-15, matlab, 5265KB, 下载27次)

http://www.pudn.com/Download/item/id/1526324392429592.html

[VHDL/FPGA/Verilog] main

完整的GMSK调制及维特比译码,程序中包括了高斯滤波器的设计,调制相位的计算,并采用了维特比译码算法解调出原始码元,最后计算了其误码率。
Complete GMSK modulation and Viterbi decoding, the program includes a Gaussian filter design, the calculation of the phase modulation, and uses the Viterbi algorithm demodulates the source element, the final calculation of the bit error rate. (2013-09-04, matlab, 4KB, 下载90次)

http://www.pudn.com/Download/item/id/2347222.html

[VHDL/FPGA/Verilog] M_M

此为数学形态滤波器消燥的代码,用于一维信号,涉及一个具体的例子,需要的话可以自己修改,修改相应的结构元素。
This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements (2013-08-29, matlab, 1KB, 下载104次)

http://www.pudn.com/Download/item/id/2342704.html

[VHDL/FPGA/Verilog] SCME-2006-08-30

3GPP空间信道模型 (扩展),该程序产生信道滤波器抽头,离散信号与其卷积,即表明信号通过该信道。
SCM 3GPP Spatial Channel Mode(extended). The program produce channel filter taps. Then,discrete signal do convolution operation with taps, which indicates that signal is through this channel. (2013-07-02, matlab, 405KB, 下载7次)

http://www.pudn.com/Download/item/id/2294079.html

[VHDL/FPGA/Verilog] bditong

用matlab实现巴特沃斯低通滤波器的M文件。本例读取电脑自带的XP开机声音,加上高频噪声,然后滤波看效果。
Butterworth low-pass filter using matlab M-file. This case, read the computer comes with XP start-up sound, coupled with high-frequency noise, and then filter to see the effect. (2013-05-11, matlab, 1KB, 下载17次)

http://www.pudn.com/Download/item/id/2238226.html

[VHDL/FPGA/Verilog] the-design-of-Four-band-filter-banks

四带滤波器组的matlab实现代码,内含正确的仿真结果 及详细标注,新手可以参考。
Four-band filter bank matlab code contains the correct simulation results and detailed labeling, can refer to the novice. (2013-04-09, matlab, 14KB, 下载40次)

http://www.pudn.com/Download/item/id/2192707.html

[VHDL/FPGA/Verilog] lowpass

低通滤波器(由matlab和simulink两种方法实现)源文件及图片示例
Low-pass filter) source file and photo examples (by the two methods matlab and simulink (2013-03-13, matlab, 403KB, 下载138次)

http://www.pudn.com/Download/item/id/2158225.html

[VHDL/FPGA/Verilog] band-reject-filters

本文利用非谐振节点技术来设计,合成带阻滤波器
In-line pseudoelliptic band-reject filters with nonresonating nodes (NRNs) and/or phase shifts are introduced. It is shown that general band-reject filters with arbitrarily placed reflection zeros (RZs) can be designed by both classes. A more general low-pass network, which contains both NRNs and phase shifts, is introduced. (2013-03-12, matlab, 573KB, 下载5次)

http://www.pudn.com/Download/item/id/2156939.html

[VHDL/FPGA/Verilog] PCM-2ASK

通信原理 PCM编码 汉明码编码 2ASK的调制与解调
Communication Theory PCM coded Hamming code to coding 2ASK of modulation and demodulation (2013-03-03, matlab, 3KB, 下载14次)

http://www.pudn.com/Download/item/id/2145865.html

[VHDL/FPGA/Verilog] weina

信号处理的目的就是要得到不受干扰影响的真正信号。相应的处理系统称为滤波器。这里,我们只考虑加性噪声的影响。
The purpose of the signal processing is to obtain undisturbed affect the real signal. Corresponding to the processing system is called a filter. Here, we consider only the impact of the additive noise. (2012-11-27, matlab, 110KB, 下载2次)

http://www.pudn.com/Download/item/id/2062585.html

[VHDL/FPGA/Verilog] scv_peak_search

该程序是从示波器产生的数据文件(.scv)中读取数据并进行DTFT分析,找出数据的频率峰值。
The program data file is generated from the oscilloscope (SCV) to read data and the DTFT analysis to identify the peak of the frequency of data. (2012-11-04, matlab, 1KB, 下载13次)

http://www.pudn.com/Download/item/id/2036912.html

[VHDL/FPGA/Verilog] apf_bigpower

新型大功率并联混合注入式有源滤波器的研究与应用
Research and Application of New High Power Parallel Hybrid Injection Active filter (2012-10-28, matlab, 231KB, 下载47次)

http://www.pudn.com/Download/item/id/2029380.html

[VHDL/FPGA/Verilog] matlab

里面包含了三段代码,主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声,然后计算其数字特征及对这些信号进行频谱分析和功率谱分析,里面还有关于低通滤波器的设计的简单说明
Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF (2012-10-15, matlab, 2KB, 下载244次)

http://www.pudn.com/Download/item/id/2016161.html

[VHDL/FPGA/Verilog] my_apll_calcoeff

在设计锁相环时,二阶环路滤波器的系数设计极为重要,本程序可以用于FPGA设计锁相环时计算所需的参数。
It is important to calculate a tow order loop filter,when designing a phase locked loop.This program can be used in designing a phase locked loop based FPGA or DSP directly. (2012-06-06, matlab, 1KB, 下载78次)

http://www.pudn.com/Download/item/id/1903884.html

[VHDL/FPGA/Verilog] DDC_Ver1.0

数字下变频(DDC)在如今基于软件无线电的架构中对系统的整体性能决定性的影响,代码为基于Matlab的4通道DDC程序,程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值
Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value (2010-08-04, matlab, 2KB, 下载131次)

http://www.pudn.com/Download/item/id/1259648.html

[VHDL/FPGA/Verilog] verilog

verilog语言例题集锦 包含加法器,乘法器,串并转换器等verilog源代码
Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code (2009-07-04, matlab, 111KB, 下载257次)

http://www.pudn.com/Download/item/id/831586.html

[VHDL/FPGA/Verilog] adaptive

这是基于MATLAB编程实现自适应滤波器,并在XILINX的FPGA上硬件可实现的模型文件
This is based on the MATLAB programming adaptive filter, and the XILINX' s FPGA hardware can be a model document (2009-06-24, matlab, 1080KB, 下载85次)

http://www.pudn.com/Download/item/id/819683.html

[VHDL/FPGA/Verilog] PhaseNoise

小数分频技术解决了锁相环频率合成器中的频率分辨率和转换时间的矛盾, 但是却引入了严重的相位噪声, 传统的相位补偿方法由于对Aö D 等数字器件的要求很高并具有滞后性实现难度较大。$2 调制器对噪声具有整形的功 能, 因而将多阶的$2 调制器用于小数分频合成器中可以很好地解决他的相位噪声的问题, 大大促进了小数分频技术的 发展和应用。文章最后给出了在GHz 量级上实现的这种新型小数分频合成器的应用电路, 并测得良好的相噪性能。
Fractional-N technology to solve the PLL frequency synthesizer in the frequency resolution and conversion time of contradictions, but the introduction of a serious phase noise, the traditional method of phase compensation A? D because of the number of devices, such as demanding and have the lag is more difficult to achieve. $ 2 modulator with noise shaping function, and thus will be more than the $ 2-order modulator for fractional-N synthesizer can be a good solution to his problem of phase noise, contributed significantly to the fractional-N technology development and applications. Finally, the article in the GHz order to achieve this new fractional-N synthesizer of the application circuit, and measured a good phase noise performance. (2008-12-09, matlab, 280KB, 下载49次)

http://www.pudn.com/Download/item/id/600487.html
总计:362