设计和验证8位MIPS处理器，集成指令寄存器、控制FSM、寄存器文件、ALU、ALU控制和程序计数器等模块。采用Verilog进行RTL设计，密切反映UVM环境的功能和验证方法。用Virtuoso制作示意图和布局。
Design and verification of a 8-bit MIPS processor, integrating modules such as the Instruction Register, Control FSM, Register File, ALU, ALU Control, and Program Counter. Employed Verilog for RTL design , closely mirroring the functionalities and verification approaches to UVM environments. Crafted schematics and layouts with Virtuoso. (2024-02-24, Verilog, 0KB, 下载0次)
Ring Johnson计数器的Verilog代码。
Verilog code for Ring-Johnson Counter. (2023-12-29, Verilog, 0KB, 下载0次)
写在FPGA上的多核协处理器
Multicore coprocessor, written on FPGA (2021-11-10, Verilog, 7351KB, 下载0次)
Xilinx FPGA的部分重构控制器
Partial Reconfiguration Controller for Xilinx FPGAs (2012-09-13, Verilog, 69KB, 下载0次)
用于FPGA的简单RISC-V处理器
Simple RISC-V processor for FPGAs (2023-04-18, Verilog, 45KB, 下载0次)
简单测试fpga比特币挖矿器
Simple test fpga bitcoin miner (2020-05-02, Verilog, 162KB, 下载0次)
sub-25-ns-nasdaq-itch-fpga解析器，，
sub-25-ns-nasdaq-itch-fpga-parser,, (2021-03-25, Verilog, 209KB, 下载0次)
fLaC编解码器的FPGA实现
Implementation of fLaC encoder decoder for FPGA (2018-10-31, Verilog, 1743KB, 下载0次)
类似于MIPS的处理器（使用VHDL）
Processor similar to MIPS (using VHDL) (2023-02-08, Verilog, 5KB, 下载0次)
约翰现场可编程JPEG压缩器；用verilog编写的jpeg压缩器。目前计划部署到Latt...
John s Field-Programmable JPEG Compressor; a jpeg compressor written in verilog. Currently targeted to deploy to Lattice s iCE40 up5k fpga. (2022-03-08, Verilog, 394KB, 下载0次)
PIC16C5x兼容FPGA处理器核心（Verilog-2001）
PIC16C5x-compatible FPGA Processor Core (Verilog-2001) (2014-04-07, Verilog, 14KB, 下载0次)
Risc-V处理器的Verilog说明
Verilog description of the Risc-V processor (2019-03-11, Verilog, 1117KB, 下载0次)
机器人应用处理器
Robotic Application Processor (2022-01-02, Verilog, 104KB, 下载0次)
8051微控制器（Verilog）的FPGA实现
FPGA implementation of the 8051 Microcontroller (Verilog) (2014-09-27, Verilog, 17KB, 下载0次)
流水线ARM7TDMI处理器在Verilog中的实现
Implemetation of pipelined ARM7TDMI processor in Verilog (2018-04-19, Verilog, 3774KB, 下载0次)
实现32位累加器功能，外部输入的信号位宽为32位
The function of 32-bit accumulator is realized, and the signal bit width of external input is 32 bits (2020-02-29, Verilog, 3KB, 下载1次)
verilog CIC filter 后面这些话就是为了凑够20字
verilog CIC filter,Wods follwed used to satisfy 20 words limition (2018-09-06, Verilog, 1332KB, 下载5次)
sdram控制器，基础资料以及常用芯片手册
some article about sdram controller, basic datasheet (2018-04-13, Verilog, 17KB, 下载9次)
器件EP4CE6F22C8N2选一数据选择器
Choose device EP4CE6F22C8N2 data selector (2018-01-16, Verilog, 68KB, 下载1次)
移位寄存器的详细剖析，经过具体的仿真和优化，发现代码完全可用
The detailed analysis of the shift register, through concrete simulation and optimization, found that the code was fully available (2017-09-21, Verilog, 55KB, 下载2次)