清华大学电子系 THUEE 2023年夏季学期数逻实验大作业-流水线处理器 Final Assignment (Summer Semester) for Digital Logic and Processor Experiment - Pipeline CPU,
Final Assignment (Summer Semester) for Digital Logic and Processor Experiment - Pipeline CPU, (2023-09-22, Verilog, 0KB, 下载0次)
MIPS（无互锁流水线级的微处理器）是精简指令集计算机（RISC）指令集架构...，
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA). This is the design of a MIPS microarchitecture that executes instructions in a single cycle. (2023-08-31, Verilog, 0KB, 下载0次)
u[Dark]RISC--“micro-darkrisc”--在DarkRISCV之前定义的早期16位微RISC处理器，
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV, (2023-07-25, Verilog, 0KB, 下载0次)
该存储库包含使用Verilog设计FPU并使用synopsys设计编译器合成FPU的自我工作。，
This repository contains self work to design FPU using Verilog and synthesize it using synopsys design compiler., (2020-07-27, Verilog, 0KB, 下载0次)
集成Berkeley hardfloat的,可以直接用于RISC-V处理器单精度 FPU 实现的小模块,
It is a small module integrated with Berkeley hardflat and can be directly used for RISC-V processor single precision FPU implementation, (2023-03-05, Verilog, 0KB, 下载0次)
在多周期处理器中实现PowerPC汇编指令集，该指令集读取机器代码并产生所需的结果...，
Implemented the PowerPC assembly instruction set in a multi-cycle processor that read the machine code and produced the desired outcome from the resulting instructions (2016-11-24, Verilog, 0KB, 下载0次)
一个完全流水线MIPS启发的32位处理器，具有分支检测和转发。支持32位IEEE-754浮点指令。，
A fully pipelined MIPS -inspired 32-bit processor with branch detection and forwarding. Supports 32-bit IEEE-754 floating point instructions., (2018-10-07, Verilog, 0KB, 下载0次)
单周期MIPS处理器项目2021-1课程EEE3530计算机体系结构的实现与仿真延世大学，
Implementation and Simulation of Single Cycle MIPS Processor Project 2021-1 Course EEE3530 Computer Architecture Yonsei University, (2021-06-17, Verilog, 0KB, 下载0次)
Altera（英特尔）Cyclone V板的MIPS处理器设计和实现。为主板提供自己的配置文件。合成和电流...，
MIPS Processor design and implementation for an Altera (intel) Cyclone V board. Provide own config file for board. Synthesizes and currently outputs fibonacci numbers on the board, but can run any MIPS instructions. (2016-09-06, Verilog, 0KB, 下载0次)
从概念到布局的设计，包括测试台，以验证无联锁微处理器简化版本的操作...，
Design from concept to layout including the testbench to verify the operation of simplified version of a Microprocessor without Interlocked Pipeline Stages (MIPS) processor and create the gate level structure followed by physical design that covers floorplanning, power mesh, clock tree synthesis, nanorouting, post-routing timing optimization (2019-05-06, Verilog, 0KB, 下载0次)
五级流水线MIPS处理器的Verilog源文件。设计用于利用ROM运行指令和危险的测试台...，
Verilog source files for a five stage pipelined MIPS processor. Testbench designed to utilize ROM to run instructions and hazards with parallel system checks. (2022-06-11, Verilog, 0KB, 下载0次)
使用Verilog HDL实现32位MIPS处理器，具有5级管道和指令数据缓存等高级功能。，
Implementation of a 32-bit MIPS processor using Verilog HDL with advanced features like a 5-stage pipeline and instruction data caches., (2023-05-10, Verilog, 0KB, 下载0次)
一种双问题超标量流水线MIPS体系结构，包括缓存、分支目标缓冲区和乘法协处理器。通信...，
A dual-issue superscalar pipelined MIPS architecture which includes a cache, a branch-target buffer and a multiplication coprocessor. Completed in ECE154B in Spring 2016 with my partner Tristan Seroff. (2017-07-28, Verilog, 0KB, 下载0次)
这是非流水线MIPS处理器的Verilog硬件描述，其中包含执行2x2矩阵乘法的指令，
This is a Hardware Description in Verilog of a non-pipelined MIPS processor with instructions to perform a 2x2 Matrix Multiplication, (2019-08-28, Verilog, 0KB, 下载0次)
在TSMC.18um工艺中设计了一个微芯片，包括一个mipscpu（8位）和一个脉动阵列加速器，
Design a micro chip in TSMC .18um process, including a mips cpu (8 bit) and a systolic array accelerator, (2023-03-05, Verilog, 0KB, 下载0次)
基于MIPS的5级流水线CPU，具有4个转发路径、暂停、标准CP0协处理器和缓存改进。，
A MIPS -based 5-stage Pipeline CPU with 4 forwarding paths, stalls, standard CP0 co-processor, and cache improvement., (2020-12-15, Verilog, 0KB, 下载0次)
32位Mips处理器是在Quartus II中使用结构化Verilog编写的。它有14条指令和256KB的数据内存。，
32 bit Mips processor is written by using structural Verilog in Quartus II. It has 14 instructions and 256KB of data memory., (2021-09-25, Verilog, 0KB, 下载0次)
MIRRORSWAMP是一个能够引导linux的MIPS处理器，它专门针对DDR3内存访问模式进行了优化。，
MIRRORSWAMP is a MIPS processor capable of booting linux, and it is specially optimized for DDR3 memory access pattern., (2019-08-20, Verilog, 0KB, 下载0次)
UM-SJTU JI.的航向VE370（FA2020）的具有危险检测的MIPS流水线处理器。，
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI., (2020-12-28, Verilog, 0KB, 下载0次)
清华大学EE数字逻辑与处理器基础实验课程的一个简单的MIPS CPU，
a simple MIPS CPU for the Fundamental Experiment of Digital Logic and Processor course of EE, Tsinghua University, (2019-10-16, Verilog, 0KB, 下载0次)