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按平台查找All Verilog(384) 

[嵌入式/单片机/硬件编程] mux21

FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件,它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较,FPGA/CPLD的规模比较大,它可以替代几十甚至几千块通用IC芯片。这样的FPGA/CPLD实际上就是一个子系统部件。 本次EDA课程设计就是利用VerilogHDL来设计设计一个2选1多路选择器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component. This EDA course design is to use Verilog HDL to design a 2-out-of-1 multiplexer (2020-05-11, Verilog, 1KB, 下载0次)

http://www.pudn.com/Download/item/id/1589204451683250.html

[嵌入式/单片机/硬件编程] count4

FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件,它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较,FPGA/CPLD的规模比较大,它可以替代几十甚至几千块通用IC芯片。这样的FPGA/CPLD实际上就是一个子系统部件。 本次EDA课程设计就是利用VerilogHDL来设计设计一个4位加法器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component. This EDA course design is to use Verilog HDL to design a 4-bit adder (2020-05-11, Verilog, 1KB, 下载0次)

http://www.pudn.com/Download/item/id/1589204210963267.html

[嵌入式/单片机/硬件编程] main

利用 CPLD 器件和实验开发板,设计并实现一个抽油烟机控制器.1.抽油烟机的基本功能只有两个:排油烟和照明,两个功能相互独立互不影响。 2.用 8×8 双色点阵模拟显示烟机排油烟风扇的转动,风扇转动方式为如图所示的四个 点阵显示状态,四个显示状态按顺序循环显示。风扇转动速度根据排油烟量的大小 分为 4 档,其中小档的四个显示状态之间的切换时间为 2 秒,中档为 1 秒,大档为 0.5 秒,空档时风扇静止不动(即停止排油烟),通过按动按键 BTN6来实现排油烟 量档位的切换,系统上电时排油烟量档位为空档,此后每按下按键 BTN6一次,排油烟量档位切换一次,切换的顺序为:空档→小档→中档→大档→空档,依次循环。
Using CPLD device and experimental development board, a controller of the range hood is designed and implemented. (2019-11-19, Verilog, 6847KB, 下载0次)

http://www.pudn.com/Download/item/id/1574154540308159.html

[嵌入式/单片机/硬件编程] dr6—ise-F

用FPGA开发板的按键作为电子表的时间初值设置控制信号,数码管当前时间值输出。用按键选择分别输出:分、秒、1/10秒。
With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds. (2017-10-11, Verilog, 331KB, 下载2次)

http://www.pudn.com/Download/item/id/1507727995373444.html