开源DDR3控制器
Open-sourced DDR3 controller (2024-03-25, Verilog, 0KB, 下载0次)
一组用于FPGA设计的教育和实用Verilog模块,在Delite FPGA MAX 10上使用Intel Quartus和ModelSim进行测试。包括时钟分频器、去噪器、解码器、状态机等实用程序。
A collection of educational and practical Verilog modules for FPGA design, tested on Delite FPGA MAX 10 with Intel Quartus and ModelSim. Includes utilities like Clock Dividers, Debouncers, Decoders, State Machines, and more. (2024-03-05, Verilog, 0KB, 下载0次)
使用verilog和pipline的Mips处理器代码
Mips processor code using verilog with pipline (2024-02-22, Verilog, 0KB, 下载0次)
基于FPGA的PCM过采样FIR滤波器。
FPGA based PCM oversampling FIR filter. (2023-12-03, Verilog, 0KB, 下载1次)
简单处理器Verilog设计中的HDL设计
HDL design in Verilog design for simple processor (2023-10-30, Verilog, 0KB, 下载0次)
Verilog HDL上的RF编解码器,
RF Codec on Verilog HDL, (2017-06-06, Verilog, 0KB, 下载0次)
Bluespec SystemVerilog(BSV)中的可合成CORDIC处理器,
Synthesizeable CORDIC processor in Bluespec SystemVerilog (BSV), (2022-09-03, Verilog, 0KB, 下载0次)
CDC路径中使用的基本同步器(Verilog),
basic synchronizers used in CDC paths ( Verilog), (2023-07-20, Verilog, 0KB, 下载0次)
用于fpga的定点卡尔曼滤波器
Fixed Point Kalman filter for fpga (2020-05-10, Verilog, 121KB, 下载2次)
基于FPGA的任天堂娱乐系统仿真器
FPGA-based Nintendo Entertainment System Emulator (2022-06-28, Verilog, 1346KB, 下载0次)
用于FPGA的OV7670(Verilog HDL)驱动器
OV7670 (Verilog HDL)Drive for FPGA (2019-03-04, Verilog, 2984KB, 下载0次)
Verilog上的TCAM(三元内容寻址存储器)
TCAM ( Ternary Content-Addressable Memory) on Verilog (2020-11-22, Verilog, 151KB, 下载0次)
Verilog实现的加减法功能计数器,通过独立的自增自减信号控制计数器进行自增计数和自减计数
Function counter of addition and subtraction implemented by Verilog (2019-11-27, Verilog, 42KB, 下载1次)
FIR滤波器的实现,verilog语言,应用folding+pipeline+unfolding+retiming硬件优化技术,参数确定用MATLAB——fertool模块进行确定。
The realization of FIR filter, Verilog language, the application of folding + pipeline + unfolding + retiming hardware optimization technology, parameter determination using MATLAB - fertool module to determine. (2019-06-08, Verilog, 1167KB, 下载4次)
实现多路可变时分复用,包括复接器,解复接,比特同步,帧同步,分频器
Implement multi-channel variable time division multiplexing, including multiplexer, demultiplexing, bit synchronization, frame synchronization, frequency divider (2018-09-16, Verilog, 18KB, 下载4次)
出租车计费,器设计一个出租车自动计费器,计费包括起步价、行车里程计费、停止和暂停不计费三部分。现场模拟汽车的启动、停止、暂停和换挡状态。分别用四位数码管显示金额和里程,各有两位小数,行程 3公里内,起步费为6元,超过3公里,以每公里1.3元计费
Car repair billing device (2018-05-04, Verilog, 1524KB, 下载8次)
xilixnx FPGA 驱动640*480显示器显示红绿蓝色条,并在左上角显示一幅200*200像素图片
Xilixnx FPGA drives 640*480 display to display red, green and blue stripe. (2018-04-28, Verilog, 4085KB, 下载4次)
SD卡控制器,用verilog编写,可以完成高速传输
SD card controller, written in Verilog, can complete high speed transmission (2017-12-12, Verilog, 2232KB, 下载14次)
《四则运算小计算器设计过程实录》第二天相关程序。更多程序请点我的账号进行下载。
7 rar documents in total.more code on this book plz put a eye on my account. (2017-07-21, Verilog, 3KB, 下载4次)
用verilog语言实现的模为60的计数器,经编译合格,利用quarter2及以上可以直接使用
Using Verilog language to achieve the modulus of 60 counters, compiled by qualified, using quarter2 and above can be used directly (2017-07-11, Verilog, 268KB, 下载1次)