在Altera DE1开发板上使用verilog hdl代码合成通用微处理器（GPM）。处理器用于查找...，
Synthesize a general purpose microprocessor (GPM) using verilog hdl code on Altera DE1 development board. The processor was used to find the greatest common divisor (GCD) between two integers. (2023-09-07, Verilog, 0KB, 下载0次)
FPGA中的实时PCM到DSD转换器
Realtime PCM to DSD converter in FPGA (2022-01-14, Verilog, 601KB, 下载2次)
基于FPGA的SVM流量分类器
FPGA-based traffic classifier using the SVM algorithm (2023-05-30, Verilog, 110KB, 下载0次)
基于FPGA的C64加速器类C65计算机
FPGA-based C64 Accelerator C65 like computer (2017-11-14, Verilog, 1149KB, 下载0次)
基于VHDL和Verilog的CAN 2.0B控制器
CAN 2.0B Controller in VHDL and Verilog (2023-04-28, Verilog, 5457KB, 下载2次)
适用于DE10 Lite的简单SDRAM控制器。
Simple SDRAM Controller for DE10-Lite. (2019-01-20, Verilog, 42KB, 下载0次)
在Verilog中实现的通用异步收发器（UART）。
A Universal asynchronous receiver transmitter (UART) implemented in Verilog. (2022-08-19, Verilog, 15KB, 下载0次)
MIPS多周期处理器在Verilog中的实现。
Implementation of a MIPS Multicycle processor in Verilog. (2013-07-06, Verilog, 1474KB, 下载0次)
LEGv8处理器的Verilog实现
A Verilog implementation of a LEGv8 Processor (2019-05-19, Verilog, 3701KB, 下载0次)
FPGA多核处理器的实现
FPGA Many-core Processor Implementation (2022-12-17, Verilog, 92KB, 下载0次)
Verilog FPGA代码：包括实验DSP音频处理器
Verilog FPGA code : including experimental DSP audio processor (2020-12-01, Verilog, 336KB, 下载0次)
用于FPGA的可编程多路ADPCM解码器
Programmable multichannel ADPCM decoder for FPGA (2020-12-28, Verilog, 247KB, 下载0次)
一种在Verilog中实现的i2c主控制器
An i2c master controller implemented in Verilog (2017-07-26, Verilog, 3KB, 下载0次)
5级流水线MIPS-32处理器
5 stage pipelined MIPS-32 processor (2020-04-20, Verilog, 1867KB, 下载0次)
用Verilog编写的DDR2内存控制器
DDR2 memory controller written in Verilog (2012-02-28, Verilog, 34KB, 下载0次)
演示数字滤波器的集合
A collection of demonstration digital filters (2022-03-11, Verilog, 175KB, 下载0次)
采样cyclone4 实现3-8译码器功能
Realize 3-8 decoder function (2020-05-22, Verilog, 5218KB, 下载0次)
用于温度传感器DS18B20的verilog程序
Verilog Program for Temperature Sensor DS18B20 (2019-01-10, Verilog, 3KB, 下载2次)
设计一个具有同步置1，异步清零的D触发器。
设计一个类似74LS160的计数器
Design an D trigger with synchronous reset 1 and asynchronous reset.
Design a counter like 74LS160. (2018-11-18, Verilog, 47KB, 下载6次)
基于Verilog编写的带SPI接口的控制器，支持SD2.0，可增加其他功能
sd controllor with spi interface witch is based on verilog,it supports SD1.0 SD2.0,user can also add other function. (2018-06-08, Verilog, 2494KB, 下载3次)