BIL265-使用Verilog的Basys 3项目计算器
BIL265 - Calculator on Basys 3 Project using Verilog (2024-03-20, Verilog, 0KB, 下载0次)
使用Verilog HDL和Python脚本创建处理器。
Creating a processor using Verilog HDL & a Python script. (2024-01-02, Verilog, 0KB, 下载0次)
用于FPGA的AXI DDR3 SDRAM控制器，
An AXI DDR3 SDRAM controller for FPGA, (2023-09-29, Verilog, 0KB, 下载0次)
一个简单的JPEG2000硬件编码器，
A simple JPEG2000 hardware encoder, (2020-09-29, Verilog, 0KB, 下载0次)
该项目旨在设计一个功能齐全的计算机处理器和存储器。这个项目使我能够探索复杂的通信...，
This project was to design a fully functional computer processor and memory. This project allowed me to explore the complexity of the computer processor and the number of states it takes for a computer to do a simple arithmetic operation. In order to complete this project, Verilog HDL was used to create a computer processor and its components. (2017-06-05, Verilog, 0KB, 下载0次)
Verilog HDL设计的DQPSK调制解调器，
DQPSK Modem designed by Verilog HDL, (2023-05-29, Verilog, 0KB, 下载0次)
ESR光谱仪控制器（Quartus HDL设计），
ESR spectrometer controller (Quartus HDL design), (2021-04-05, Verilog, 0KB, 下载0次)
步进电机控制器的FPGA HDL代码，
The FPGA HDL code for the stepper motor controll, (2017-05-04, Verilog, 0KB, 下载0次)
Verilog中的32位单周期MIPS处理器，
32-bit Single Cycle MIPS Processor in Verilog, (2023-08-16, Verilog, 0KB, 下载0次)
该存储库包含同步逻辑组件的设计和模拟，如D-Latch、D触发器、4位移位寄存器、...，
This repository contains the design and simulation of synchronous logic components such as D-Latch, D Flip-Flop, 4-Bit Shift Register, and a 4-Bit Synchronous Parallel Load Shift Register with Counter, all implemented using Verilog HDL. (2023-07-28, Verilog, 0KB, 下载0次)
升级SchoolMIPS单核处理器
Upgrade of SchoolMIPS single-core processor (2023-03-09, Verilog, 4KB, 下载0次)
用于更快SWD编程的fpga协处理器
fpga co-processor for faster SWD programming (2017-09-16, Verilog, 151KB, 下载0次)
DLX处理器的实施和改进
DLX processor implementation and improvement (2017-07-18, Verilog, 6819KB, 下载0次)
假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）
Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset). (2019-01-22, Verilog, 7KB, 下载14次)
vivado fir滤波器（运用MATLAB工具）
Vivado FIR filter(Using MATLAB tools) (2018-11-07, Verilog, 4234KB, 下载11次)
简单计算器能实现4位二进制数的加减乘除，并以数码管进行显示。
Simple calculator can realize the addition and subtraction multiplication and division of 4 bit binary number, and display it by digital tube. (2018-06-25, Verilog, 19730KB, 下载6次)
LS165移位寄存器的verilog语言编写
The writing of the Verilog language of LS165 shift register (2018-02-28, Verilog, 361KB, 下载2次)
全加器，可以实现数据的加法运算，有来自低位的进位和向高位的进位。
Full adder, data can be added to the operation, there are low from the carry and to the high carry. (2017-10-11, Verilog, 158KB, 下载3次)
一个用quartus原理图输入的全加器，
A full adder with quartus schematic input, (2017-10-03, Verilog, 1KB, 下载2次)
《四则运算小计算器设计过程实录》第三天相关程序。更多程序请点我的账号进行下载。
7 rar documents in total.more code on this book plz put a eye on my account. (2017-07-21, Verilog, 4KB, 下载5次)