在硬件描述语言的帮助下，设计了全减法器和半减法器。此外，该项目还涵盖了设计段落...，
With the help of hardware description language, I ve designed full and half subtractor. Also, this project covers the way to design parallel subtractor using Verilog. (2023-10-11, Verilog, 0KB, 下载0次)
使用比较器单元进行比较的封装寄存器，取决于输出符号是否大于、小于或等于t...，
Encompassed registers which were compared using comparator unit , depending upon the output sign if it was greater , less than or equal to , generated an output which computed the result considering the FSM chart and various states that were required for the perfect sequencing of operations .Designed in Xilinx VIVADO tool using Verilog HDL. (2022-03-10, Verilog, 0KB, 下载0次)
从code.google.com p vhdl助听器自动导出
Automatically exported from code.google.com p vhdl-hearing-aid (2015-06-30, Verilog, 26641KB, 下载0次)
一个用Verilog编写的脑洞原生软处理器。
A brainfuck-native soft processor written in Verilog. (2021-01-07, Verilog, 886KB, 下载0次)
简单的FPGA双通道示波器（Spartan3、Verilog、Picoblaise）
Simple FPGA dual channel oscilloscope (Spartan3, Verilog, Picoblaze) (2014-11-27, Verilog, 11934KB, 下载0次)
为通用RGB图像设计中值滤波器。
Design a median filter for a Generic RGB image. (2019-03-06, Verilog, 1134KB, 下载0次)
流水线MIPS处理器的Verilog实现
A Verilog implementation of a pipelined MIPS processor (2017-10-20, Verilog, 429KB, 下载0次)
6502微处理器的近门级Verilog模拟。
A near gate-level Verilog simulation of the 6502 microprocessor. (2021-10-05, Verilog, 1974KB, 下载0次)
利用verilog和Matlab实现LMS自适应滤波器
LMS-Adaptive Filter implement using verilog and Matlab (2016-10-21, Verilog, 1079KB, 下载2次)
Wishbone控制的I2C控制器
Wishbone controlled I2C controllers (2023-05-15, Verilog, 426KB, 下载0次)
用Verilog编写的简单单周期RISC处理器
Simple single cycle RISC processor written in Verilog (2018-03-23, Verilog, 107KB, 下载0次)
微程序65C02兼容FPGA处理器核心（Verilog-2001）
Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001) (2016-09-18, Verilog, 5701KB, 下载0次)
循环冗余校验是一种根据网络数据包或计算机文件等数据产生简短固定位数校验码的一种散列函数，主要用来检测或校验数据传输或者保存后可能出现的错误。生成的数字在传输或者存储之前计算出来并且附加到数据后面，然后接收方进行检验确定数据是否发生变化。
Cyclic redundancy check (CRC) is a hash function that generates short fixed bit parity check codes based on network packets or computer files. It is mainly used to detect or verify errors that may occur after data transmission or storage. The generated number is calculated and appended to the data before transmission or storage, and then the receiver checks to see if the data has changed. (2020-10-20, Verilog, 2KB, 下载0次)
FIR低通滤波器
代码介绍
16bit输入信号的8阶FIR低通滤波器
V1.0 2019.11.6
输入信号位宽：16bit；
阶数：8；
Fs：10000Hz；
Fpass：1000Hz；
Fstop：3000Hz。
FIR low pass filter
Code introduction
8-order FIR low-pass filter for 16bit input signal
V1.0 2019.11.6
Input signal bit width: 16bit;
Order: 8;
Fs: 10000Hz;
Fpass: 1000Hz;
Fstop: 3000Hz. (2020-08-01, Verilog, 202KB, 下载5次)
FIR滤波器的FPGA实现，基于MATLAB和Quartus平台，使用Verilog和IP core设计，有详细的说明操作文档，并附上结果图，验证可行，欢迎学习
FPGA implementation of FIR filter, based on MATLAB and quartus platform, using Verilog and IP core design, with detailed operation documents, and attached with the result chart, verified feasible, welcome to learn (2020-02-19, Verilog, 3250KB, 下载5次)
简单编程，借助硬件输出，可实现多种功能的音乐播放
Multi-function Music Play (2020-02-17, Verilog, 6KB, 下载2次)
存放一张图片，通过FPGA读取存储器数据，通过VGA显示器显示图片，可以对实时读取或缓存，内附有完整代码，并有word文档的详细讲解。
Store a picture, read the memory data through the FPGA, display the picture through the VGA display, can read or cache in real time, with complete code, and a detailed explanation of word documents. (2019-05-30, Verilog, 31182KB, 下载3次)
quartus 17.1 安装包，我现在用的就是
Quartus 17.1 installation kit, what I am using now is (2018-09-10, Verilog, 107KB, 下载49次)
FPGA基础程序，蜂鸣器程序，入门程序。verliog程序
FPGA basic program, introductory program (2018-05-05, Verilog, 501KB, 下载0次)
说明： SDR SDRAM 控制器 来自lattice 已经分析代码可用!大家可以参考修改，形成自己的实例
Description: SDR SDRAM controller from lattice has been analyzed code available, we can refer to modify, to form their own examples (2017-09-06, Verilog, 17KB, 下载6次)