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按分类查找All VHDL/FPGA/Verilog(1148) 
按平台查找All Verilog(1148) 

[VHDL/FPGA/Verilog] Ring-and-Johnson-Counter

使用Iverilog码的环和约翰逊计数器
Ring and Johnson Counter Using Iverilog code (2024-01-18, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1705642419147153.html

[VHDL/FPGA/Verilog] Nuked-SMS-FPGA

用Verilog(WIP)编写的Sega主系统模拟器,
Sega Master System emulator written in Verilog (WIP), (2023-10-18, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1697673743369952.html

[VHDL/FPGA/Verilog] UART-protocol

使用Verilog HDL设计的通用异步收发器,
Universal Asynchronous Receiver Transmitter designed using Verilog HDL, (2023-09-16, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1695001360250215.html

[VHDL/FPGA/Verilog] Memory-Simulator

基于Verilog的集合关联缓存模拟器,
A Verilog-based Simulator of a Set-Associative Cache, (2022-11-13, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694142757764544.html

[VHDL/FPGA/Verilog] 8-bit-harvard-processor

8位哈佛处理器的veriloghdl设计,
verilog hdl design of a 8 bit harvard processor, (2020-03-19, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694141636250825.html

[VHDL/FPGA/Verilog] 16-Bit_CPU_Design

在Verilog HDL中设计、模拟和合成了一个16位CPU。该设计涉及计数器的RTL编码、ALU、CPU控制器、Instruc...,
Designed, Simulated and Synthesized a 16-Bit CPU in Verilog HDL. The design involved RTL coding for counter, ALU, CPU controller, Instruction register and data memory. (2019-02-15, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694141349788927.html

[VHDL/FPGA/Verilog] Rotary-Encoder-MK991-Driver

(Verilog)旋转编码器MK991的驱动程序 Rotary Encoder MK991 Driver,
(Verilog) Rotary Encoder MK991 Driver, (2023-08-07, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1691414159716083.html

[VHDL/FPGA/Verilog] nes260

Xilinx KV260 FPGA板的NES仿真器
NES emulator for Xilinx KV260 FPGA board (2022-07-24, Verilog, 345KB, 下载0次)

http://www.pudn.com/Download/item/id/1658617088596279.html

[VHDL/FPGA/Verilog] vga-interface-with-TANG-PRIMER-FPGA

唐底漆与VGA显示器的接口。
Interfacing Tang primer with VGA display. (2021-02-04, Verilog, 1578KB, 下载0次)

http://www.pudn.com/Download/item/id/1612432888287894.html

[VHDL/FPGA/Verilog] LASER310_FPGA

激光器310 FPGA VZ200 VZ300 DE0 DE1 DE2 MC6847
LASER310 FPGA VZ200 VZ300 DE0 DE1 DE2 MC6847 (2020-09-21, Verilog, 23354KB, 下载0次)

http://www.pudn.com/Download/item/id/1600621942554447.html

[VHDL/FPGA/Verilog] Tang-Nano_I2C_Monitor

基于Tang Nano FPGA的I2C总线监控器
I2C Bus monitor on Tang-Nano FPGA (2021-02-21, Verilog, 2862KB, 下载0次)

http://www.pudn.com/Download/item/id/1613895004592984.html

[VHDL/FPGA/Verilog] sata_2_host_controller

用于FPGA实现的Sata 2主机控制器
Sata 2 Host Controller for FPGA implementation (2017-10-11, Verilog, 209KB, 下载0次)

http://www.pudn.com/Download/item/id/1507707197305978.html

[VHDL/FPGA/Verilog] iceGDROM

世嘉Dreamcast的基于FPGA的GDROM仿真器
An FPGA based GDROM emulator for the Sega Dreamcast (2023-02-18, Verilog, 363KB, 下载0次)

http://www.pudn.com/Download/item/id/1676723450591667.html

[VHDL/FPGA/Verilog] DLX

用VHDL语言建立DLX处理器的功能模型
Building a functional model of the DLX processor with VHDL (2018-11-06, Verilog, 35838KB, 下载0次)

http://www.pudn.com/Download/item/id/1541485666679598.html

[VHDL/FPGA/Verilog] ax-encoder-drv

xilinx fpga LCD编码器驱动程序,有详细说明
Xilinx FPGA LCD encoder driver (2021-03-27, Verilog, 1KB, 下载1次)

http://www.pudn.com/Download/item/id/1616807512981620.html

[VHDL/FPGA/Verilog] 开源软核处理器OPENRISC的SOPC设计

《开源软核处理器OpenRisc的SOPC设计》介绍基于源代码开放的OpenRisc1200(以下简称OR1200)软核处理器的SOPC设计方法。《开源软核处理器OpenRisc的SOPC设计》分为两部分,第一部分介绍OR1200软核处理器的架构和配置、Wishbone总线的标准及OR1200软核处理器软硬件开发环境的建立;第二部分以具体实例说明如何使用OR1200软核处理器完成嵌入式设计,其中包括:调试接口的实现、OR1200控制片内存储器和I/O、串口、SDRAM、外部总线、以太网、LCD及SRAM;另外还介绍如何在OR1200上运行嵌入式Linux,并针对第二部分给出部分源代码。 《开源软核处理器OpenRisc的SOPC设计》适合对SOPC或OR1200软核处理器感兴趣的初学者使用,也可作为嵌入式系统设计人员的自学用书,或作为相关专业研究生的教材和教师的教学参考书。
Open source processor design method based on openriscor1200. The SOPC design of open source soft core processor openrisc is divided into two parts. The first part introduces the architecture and configuration of or1200 soft core processor, wishbone bus standard and the establishment of software and hardware development environment of or1200 soft core processor. The second part describes how to use or1200 soft core processor to complete embedded design with specific examples, including the implementation of debugging interface and or1200 control In addition, it introduces how to run embedded Linux on or1200, and gives some source codes for the second part. SOPC design of open source soft core processor openrisc is suitable for beginners who are interested in SOPC or or1200 soft core processor. It can also be used as a self-study book for embedded system designers, or as a teaching reference book for graduate students and teachers. (2020-10-27, Verilog, 11722KB, 下载3次)

http://www.pudn.com/Download/item/id/1603781530127775.html

[VHDL/FPGA/Verilog] 基于FPGA的图像处理加速器研究_张皓

基于FPGA的图像处理加速器设计,实现了图像处理的硬件加速,硕士论文
The design of image processing accelerator based on FPGA realizes the hardware acceleration of image processing (2020-03-18, Verilog, 3251KB, 下载2次)

http://www.pudn.com/Download/item/id/1584504482571888.html

[VHDL/FPGA/Verilog] 12jinzhi

使用quartus软件开发的12进制计数器工程文件
12-digit counter program using Quartus (2019-01-02, Verilog, 110KB, 下载0次)

http://www.pudn.com/Download/item/id/1546437801313413.html

[VHDL/FPGA/Verilog] filter_DQ+JK

Verilog实现滤波器功能,DQ+JK Filter
Verilog implements Filter function, DQ+JK Filter (2018-06-15, Verilog, 13334KB, 下载3次)

http://www.pudn.com/Download/item/id/1529032461112835.html

[VHDL/FPGA/Verilog] half_adder

verilog HDL实现一位半加器功能
Verilog HDL implements a half adder function (2018-05-05, Verilog, 2932KB, 下载0次)

http://www.pudn.com/Download/item/id/1525504906416123.html
总计:1148