32位RISC处理器的HDL设计与实现
HDL design and implementation of 32 bit RISC Processor (2024-02-08, Verilog, 0KB, 下载0次)
用Verilog实现的玩具式MIPS32 CPU模拟器
A toy MIPS32 CPU simulator implemented in Verilog (2023-12-01, Verilog, 0KB, 下载0次)
系统verilog中的RTL数据路径和控制器,
RTL Datapath and Controller in system verilog, (2021-03-10, Verilog, 0KB, 下载0次)
Verilog中的VGA控制器RTL(软ip),
VGA controller RTL ( soft ip ) in Verilog, (2021-05-18, Verilog, 0KB, 下载0次)
Verilog HDL中路由器的架构设计,
Architectural design of Router in Verilog HDL, (2019-12-30, Verilog, 0KB, 下载0次)
通用FPGA SDRAM控制器,最初为AS4C4M16SA制作,
Generic FPGA SDRAM controller, originally made for AS4C4M16SA, (2020-09-07, Verilog, 0KB, 下载0次)
用Verilog-2005编写的NES控制器接口,
NES Controller Interface written in Verilog-2005, (2023-09-05, Verilog, 0KB, 下载0次)
用Verilog HDL编写的fibonacci数字计算器,
fibonacci number calculator written in Verilog-HDL, (2017-02-23, Verilog, 0KB, 下载0次)
基于FPGA的RepRap型3D打印机运动控制器
FPGA based motion controller for RepRap style 3D printers (2013-05-06, Verilog, 7984KB, 下载0次)
基于Cλash Haskell FPGA的SKI演算评估器
Cλash Haskell FPGA-based SKI calculus evaluator (2016-01-09, Verilog, 37KB, 下载0次)
通过Verilog VHDL制作VGA控制器的作业
A homework of making a VGA controller via Verilog VHDL (2021-07-18, Verilog, 7074KB, 下载0次)
24位RISC处理器的实现
Implementation of a 24 bit RISC processor (2019-11-18, Verilog, 683KB, 下载0次)
基于verilog HDL开发的FPGA的CNN加速器。
CNN-Accelerator based on FPGA developed by verilog HDL. (2022-01-27, Verilog, 54642KB, 下载0次)
矢量L2范数处理器的Verilog实现
Verilog Implementation of a Vector L2 Norm Processor (2017-08-11, Verilog, 234KB, 下载0次)
流水线多层感知器(神经网络)的HDL实现
HDL implementation of a pipelined multilayer perceptron (neural network) (2015-09-14, Verilog, 30KB, 下载0次)
单周期RISC MIPS处理器
Single Cycle RISC MIPS Processor (2021-09-17, Verilog, 463KB, 下载0次)
增强型6502 65C02微程序FPGA处理器核心(Verilog-2001)
Enhanced 6502 65C02 Microprogrammed FPGA Processor Core (Verilog-2001) (2022-03-15, Verilog, 4642KB, 下载0次)
一个用verilog编写的非常简单的VGA控制器
A very simple VGA controller written in verilog (2012-06-01, Verilog, 2KB, 下载0次)
verilog中数据路由器的体系结构设计
Architectural design of data router in verilog (2019-12-29, Verilog, 5942KB, 下载0次)
展望未来,用Verilog编写的参数化仲裁器。
A look ahead, round-robing parametrized arbiter written in Verilog. (2020-05-22, Verilog, 9KB, 下载0次)