这是verilog中的解码器代码（带测试台）
This is decoder code(with test bench) in verilog (2024-04-01, Verilog, 0KB, 下载0次)
这是verilog中的编码器代码（带测试台）
This is encoder code(with test bench) in verilog (2024-04-01, Verilog, 0KB, 下载0次)
采用Verilog HDL设计了16级8位数据宽度FIFO存储器，采用先进先出（FIFO）存储器芯片对应用程序进行缓冲...，
Designed 16 stages and 8-bit data-width FIFO memory using Verilog HDL. First-in, first-out (FIFO) memory chips are used in buffering applications between devices that operate at different speeds or in applications where data must be stored temporarily for further processing. (2021-07-02, Verilog, 0KB, 下载0次)
带有自检测试台的Verilog设计示例。半加法器，全加法器，多路复用器，ALU，D触发器，序列检测器...
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous (2022-10-10, Verilog, 72KB, 下载0次)
基于verilog HDL开发的FPGA的CNN加速器。
CNN-Accelerator based on FPGA developed by verilog HDL. (2020-04-10, Verilog, 134KB, 下载0次)
出租车计费程序，基于Verilog，QuartusII
Based on Verilog,Quartus II Taxi billing procedures full code. (2021-03-28, Verilog, 6KB, 下载0次)
基于verilog的驱动温湿度传感器dht11代码
DHT11 code of driving temperature and humidity sensor based on Verilog (2020-12-19, Verilog, 1280KB, 下载1次)
进行ppm编解码的verilog代码，RTL描述
Verilog code for ppm encoding and decoding, RTL description (2020-12-08, Verilog, 28KB, 下载14次)
38译码器代码，适合初学Verilog语言，带仿真文件，亲测可用
38 decoder code With simulation file (2020-08-20, Verilog, 270KB, 下载0次)
3-8编码器，基于verilog实现，初级程序
3-8encoder,Based on Verilog implementation,the primary program (2019-10-03, Verilog, 3KB, 下载0次)
VGA驱动的verilog代码 实现滚动彩条
VGA Driver for Rolling Color Bars (2019-06-17, Verilog, 4KB, 下载2次)
用Verilog编程，在SWORD板上实现计分器
ScoreBoard on Sword, using Verilog (2019-02-27, Verilog, 289KB, 下载8次)
fpga基础源发及时序仿真 包涵状态机设计思路 3-8译码器 BCD计数器 按键消抖 红外接收 RS485 收发器 SDRAM DAC ADC led1602显示模块 等基本模块程序
FPGA basic source generation and timing simulation includes State machine design ideas 3 - 8 decoder BCD counter key anti-shake infrared receiver RS485 transceiver SDRAM DAC ADC LED 1602 display module and other basic module programs (2018-11-26, Verilog, 43190KB, 下载5次)
采用Basys3开发平台外接蜂鸣器， 利用系统时钟进行分频和音符时长的控制，LED灯随乐曲节奏律动。
Based on Basys3 connected with speaker, we use clock to control the music, LEDs shining with the melody (2018-10-06, Verilog, 537KB, 下载0次)
I2C主设备(IIC Master) FPGA源码, Verilog写的
I2C Master device (IIC Master) for FPGA with Verilog (2018-09-11, Verilog, 13KB, 下载12次)
VGA输出彩条，通过显示器输出，三线八种颜色输出。
VGA Output colour bar (2018-06-21, Verilog, 83KB, 下载0次)
3-8线译码器，输入为3位的二进制数字，进行译码，得到有效数字
3-8 wire decoder, input to 3 bits of binary digit, carry on decoding and get effective number. (2018-04-12, Verilog, 5450KB, 下载1次)
该程序结合iic驱动程序，可用自动检测硬件的寄存器配置参数是否正确，项目中已使用过
With the IIC driver, the program can automatically detect whether the hardware's register configuration parameters are correct. The program has been used in the project. (2018-03-15, Verilog, 2KB, 下载2次)
Verilog 语言编写 PCI9054 控制器的接口电路，实现 PCI总线到本地 8 位总线的转接控制
The Verilog language writes the interface circuit of the PCI9054 controller to realize the transfer control of the PCI bus to the local 8 bit bus (2017-11-29, Verilog, 20KB, 下载15次)
详细介绍了CIC滤波器的设计及优化，并对其FPGA实现也进行了详细的分析和设计
The design and optimization of CIC filter are introduced in detail, and the implementation of FPGA is also analyzed and designed in detail (2017-10-07, Verilog, 122KB, 下载4次)