使用Verilog的简单多周期RISC处理器
Simple Multi Cycle RISC Processor Using Verilog (2024-04-27, Verilog, 0KB, 下载0次)
使用FPGA将远场图像流式传输到监视器
Stream farbfeld images to a monitor using an FPGA (2024-04-07, Verilog, 0KB, 下载0次)
RISC-V核心CI CD的控制器模块
controller module for RISC-V core CI CD (2024-02-18, Verilog, 0KB, 下载0次)
出租车计价器——一个EDA课程设计大作业
Taxi meter -- a big assignment of EDA course design (2023-12-05, Verilog, 0KB, 下载0次)
流水线SPDIF解码器和均衡器。verilog模块和tb-s，
pipelined SPDIF decoder and equalizer. verilog modules and tb s, (2023-09-28, Verilog, 0KB, 下载2次)
用Verilog硬件描述语言编写的简单SDRAM控制器，
Simple SDRAM controller written in Verilog hardware description language, (2023-09-09, Verilog, 0KB, 下载0次)
使用Verilog和Quartus II的简单8086-CPU模拟器，
A simple 8086-CPU simulator using Verilog and Quartus II, (2018-07-09, Verilog, 0KB, 下载0次)
它包含mealy和moore序列检测器verilog代码，
it contains mealy and moore sequence detectors verilog code, (2023-08-31, Verilog, 0KB, 下载0次)
基于FPGA开发的MP3播放器（DIGILENT NEXYS 4 DDR）
MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR) (2019-02-11, Verilog, 492KB, 下载0次)
基于max1000 FPGA模块的高性价比高频收发器
Cost Effective HF transceiver based on max1000 FPGA module (2021-04-07, Verilog, 5050KB, 下载0次)
这是一个用于FPGA的环形缓冲控制器。
This is a circular buffer controller used in FPGA. (2016-01-12, Verilog, 5KB, 下载0次)
DE2 FPGA平台上USB控制器的硬件接口
Hardware interface for USB controller on DE2 FPGA Platform (2021-12-24, Verilog, 5187KB, 下载0次)
用于FPGA的超大尺寸优化RV32I软处理器。
A extremely size-optimized RV32I soft processor for FPGA. (2018-06-19, Verilog, 3KB, 下载0次)
FPGA显示控制器，支持VGA、DVI和HDMI。
FPGA display controller with support for VGA, DVI, and HDMI. (2020-03-09, Verilog, 249KB, 下载0次)
基于VHDL语言设计的8位RISC微处理器
A 8-bit RISC based microprocessor designed in VHDL (2019-05-26, Verilog, 11KB, 下载0次)
用于FPGA和ASIC的VHDL MIPS处理器
A MIPS processor in VHDL for FPGA and ASIC (2016-01-12, Verilog, 24468KB, 下载0次)
一种5级流水线mips32处理器
A 5-stage pipelined mips32 processor (2017-05-09, Verilog, 603KB, 下载0次)
MiniMIPS32 五级流水线处理器 Verilog建模和Logisim建模
Verilog Modeling and Logisim Modeling for MiniMIPS32 Five Stage Pipeline Processor (2020-12-28, Verilog, 119KB, 下载0次)
一种开放源代码链路协议和控制器
An Open Source Link Protocol and Controller (2021-08-01, Verilog, 797KB, 下载0次)
FAST-9角点检测加速器
FAST-9 Accelerator for Corner Detection (2021-01-01, Verilog, 835KB, 下载0次)