基于FPGA的信号发生器
FPGA based signal generator (2015-06-25, Verilog, 8321KB, 下载0次)
高斯噪声发生器Verilog IP核
Gaussian noise generator Verilog IP core (2023-05-22, Verilog, 10986KB, 下载0次)
一个很简单的 verilog 写的 时钟 发生器，产生1us，10us，1ms ，100ms 等cllk
a simple verilog module , the module generate clk ,such as 1us 10us 1ms 10ms 100ms (2021-03-17, Verilog, 1KB, 下载0次)
FPGA函数发生器的实现，逻辑分析仪和ModelSim显示
FPGA function generator implementation, logic analyzer and Modelsim display (2020-12-26, Verilog, 179KB, 下载0次)
1，使用quartus,生成.mif文件，然后导入正弦波数据
2.利用LPM功能定制一个8bit数据宽度，128字节深度的ROM;利用MATLAB和FPGA实现基于ROM的正弦波发生器.
1. Use quartus to generate. MIF file, and then import sine wave data
2. Use LPM function to customize a ROM with 8 bit data width and 128 byte depth; use MATLAB and FPGA to realize the sine wave generator based on ROM (2020-09-16, Verilog, 2343KB, 下载2次)
AD9954 DDS开发板-点频9954(ok)
verilog 语言
AD9954 DDS demo codes (2020-03-31, Verilog, 706KB, 下载2次)
电子设计大赛题目，实现一个基本的波形发生器，并实现频率计能狗准确测量
The realization of a basic waveform generator, and the realization of frequency meter can be accurately measured dog (2020-03-13, Verilog, 17KB, 下载0次)
pwn信号发生器的源代码和仿真图，该程序可实现频率可调，占空比可调的pwm信号
Pulse generator with adjustable duty cycle (2019-12-12, Verilog, 27KB, 下载2次)
VERILOG 和电图的结合做dds 可产生正弦波 方波 锯齿波
The combination of Verilog and electrogram can produce sine wave, square wave and sawtooth wave by DDS (2019-11-28, Verilog, 230KB, 下载1次)
使用DE2实现DDS，步骤简单，配置管脚可自查看
Using DE2 to realize DDS, the steps are simple and the pins can be self-checked. (2019-07-19, Verilog, 3029KB, 下载2次)
本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出
In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output (2019-05-06, Verilog, 15402KB, 下载3次)
设计m序列发生器,其特征方程为 ，输出数字序列信号m_sequence码速率为10Mbps
Design of m-Sequence Generator (2019-03-17, Verilog, 31KB, 下载5次)
基于FPGA的两路的频率可调的正弦信号发生器，verilog语言
Two way frequency adjustable sinusoidal signal generator based on FPGA, Verilog language (2018-11-17, Verilog, 11378KB, 下载2次)
在Vivado下完成AD输入到下变频的功能，频率可配置，通用化设计。
The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design. (2018-11-15, Verilog, 5660KB, 下载19次)
基于Quartus II，DDS信号源程序
Based on Quartus II, DDS source (2018-06-01, Verilog, 4086KB, 下载1次)
基于verilog的dds实现，可以实现正弦波、三角波和锯齿波，基于ISE14.7
Verilog based DDS implementation, can achieve sine wave, triangle wave and sawtooth wave, based on ISE14.7 (2018-05-17, Verilog, 17892KB, 下载7次)
一个频率可调节的DDS。带仿真数据还有板及仿真
A frequency adjustable DDS. Simulation data, board and simulation (2018-05-03, Verilog, 6793KB, 下载4次)
基于Verilog语言实现DDS（数字频率合成器）的设计，有完整的工程设计代码和仿真脚本
Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scripts (2017-08-11, Verilog, 7330KB, 下载12次)
使用FPGA控制VGA显示波形，显示汉字，水平垂直可调
FPGA controls the VGA display waveform (2017-07-23, Verilog, 3KB, 下载6次)
FPGA 实验程序 DDS 实验程序
FPGA PROCEDURE SHANDONG UNIVERSITY (2017-07-18, Verilog, 16415KB, 下载9次)