使用Verilog的基于FPGA的链码图像编码器和解码器。使用链码算法压缩图像，并具有UART通信功能，以实现有效的数据传输。
FPGA-based Chain Code Image Encoder and Decoder using Verilog. Compresses images with chain code algorithms and features UART communication for efficient data transfer. (2024-02-04, Verilog, 0KB, 下载0次)
它集成了移位寄存器、计数器和加法器FSM逻辑单元，该逻辑单元基于输入进位和数据生成和输出信号...，
It incorporates Shift registers , counter and Adder FSM logic Unit which generates the sum output signal based upon the input carry and data from shift registers then computes the result in sum register . it was designed in Quartus Prime Lite using Verilog HDL and verified in Modedlsim. Learnt about the FSM based Design techniques in RTL design ... (2022-04-01, Verilog, 0KB, 下载0次)
DNN硬件加速器上实验室项目的SystemVerilog文件，
SystemVerilog files for lab project on a DNN hardware accelerator, (2021-06-22, Verilog, 0KB, 下载0次)
Verilog HDL中的SDRAM控制器，
A SDRAM controller in Verilog HDL, (2022-03-21, Verilog, 0KB, 下载0次)
NeoPixel LED Controller | NeoPixel LED 控制器 | 基於MAX10 FPGA的音樂全彩光立方LED控制器
NeoPixel LED Controller | NeoPixel LED Controller | Music Full Color Light Cube LED Controller Based on MAX10 FPGA (2022-01-04, Verilog, 1171KB, 下载0次)
TinyFPGA微控制器和复古计算机的开源构建块。
Opensource building blocks for TinyFPGA microcontrollers and retro computers. (2017-09-29, Verilog, 18KB, 下载0次)
基于AXI4的开源高性能HyperRAM内存控制器
Open-source high performance AXI4-based HyperRAM memory controller (2022-10-06, Verilog, 5199KB, 下载0次)
该项目是一个专用处理器的实现，该处理器可以计算最大公倍数（GCM）和...
This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode) (2019-07-18, Verilog, 82KB, 下载0次)
用Verilog实现的微处理器，用于逻辑设计实验室最终项目。
Microprocessor implemented with Verilog, for Logic Design Lab Final Project. (2018-06-12, Verilog, 6KB, 下载0次)
Verilog中实现的FPGA（非常）最小的web浏览器
A (very) minimal web browser for FPGAs implemented in Verilog (2020-04-03, Verilog, 3678KB, 下载0次)
32位浮点乘法器-累加器单元（MAC）
32 - bit floating point Multiplier Accumulator Unit (MAC) (2021-01-12, Verilog, 155KB, 下载0次)
Lattice FPGA ECP5芯片的位流到Verilog反编译器。
Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip. (2021-10-10, Verilog, 138KB, 下载0次)
Voila-Jones人脸检测器的硬件实现
A Voila-Jones face detector hardware implementation (2018-11-29, Verilog, 7138KB, 下载0次)
一种用于FPGA的叉臂控制示波器
A wishbone controlled scope for FPGA s (2021-01-26, Verilog, 462KB, 下载0次)
802.11 OFDM解码器的可合成、模块化Verilog实现。
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. (2023-01-29, Verilog, 29693KB, 下载0次)
RS-485是针对UART串口的一种接口标准，它定义了串行通信系统中发送器和接收器的一系列电气特性.
RS-485 is an interface standard for UART serial port. It defines a series of electrical characteristics of transmitter and receiver in serial communication system (2020-08-12, Verilog, 3411KB, 下载1次)
实现5级流水多周期MIPS CPU。流水线是数字系统中一种提高系统稳定性和工作速度的方法，广泛应用于高档CPU的架构中。根据MIPS处理器的特点，将整体的处理过程分为取指令（IF）、指令译码（ID）、执行（EX）、存储器访问（MEM）和寄存器写（WB）五级，对应多周期的五个处理阶段。
Implementation of 5-stage pipeline multi-cycle MIPS CPU (2019-07-06, Verilog, 3626KB, 下载8次)
24s倒计时器Verilog完整工程。管脚配置、各种settings都已设置好。
24s Countdown. Verilog. Complete Project (2019-05-30, Verilog, 5570KB, 下载0次)
verilog100进制计数器，层次结构。语言或图形顶层模块。
Verilog100 counter, hierarchy. Language or graphics top-level module. (2019-05-17, Verilog, 135KB, 下载1次)
3_8译码器就是将输入的三位编码转换为8位输出，使其中一位与其他不同，从而实现译码功能
The 3_8 decoder converts the input three bit code to 8 bit output, so that one of the bits is different from others, thus realizing the decoding function. (2018-04-28, Verilog, 2962KB, 下载1次)