上板调试过的spi程序，用singaltap抓取波形，没有问题，可在此基础上修改
SPI program debugged on board, grabbing waveform with singaltap, no problem, can be modified on this basis (2021-04-12, Verilog, 5038KB, 下载0次)
4位乘法器，实现quartusII 编程，包含项目源码以及已经生成的仿真波形
4 bit multiplier, achieve QuartusII programming, including the source code of the project and has generated the simulation waveform (2021-03-27, Verilog, 4181KB, 下载2次)
ADC9650测试程序，对ad9914生成波形进行ADC采样，可以在VIVADO2017.4上直接运行，已验证.
Adc9650 test program, ad9914 waveform generated by ADC sampling, can be run directly on vivado 2017.4, has been verified (2020-08-07, Verilog, 50851KB, 下载38次)
单周期32位RI型指令CPU，在ISE上进行波形仿真
Single cycle 32-bit RI instruction CPU, waveform simulation on ISE (2020-06-06, Verilog, 7492KB, 下载1次)
单周期32位R型指令CPU，在ISE进行波形仿真
Single cycle 32-bit R-type instruction CPU (2020-06-06, Verilog, 3901KB, 下载0次)
crc编码，在串行通信过程中通过编码减少错误发生
CRC code, in the process of serial communication by coding to reduce the occurrence of errors (2020-05-01, Verilog, 1KB, 下载1次)
在quartus上运行16QAM仿真，实现在modelsim上的波形仿真
Running 16QAM simulation on quartus (2020-04-27, Verilog, 9360KB, 下载2次)
基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。
Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core. (2020-03-29, Verilog, 11045KB, 下载2次)
双通道AD9226高速采集代码，使用逻辑分析仪观察波形。
Double channel ad9226 high-speed acquisition code, using logic analyzer to observe the waveform. (2019-12-24, Verilog, 10192KB, 下载1次)
实现cpu的构成与仿真测试，可以较为完整的展现测试波形
Realization of CPU composition and simulation test (2019-06-26, Verilog, 166KB, 下载1次)
在数字传输系统中，因为存在噪声，信道衰落等干扰因素，会使传输的信号发生错误，产生误码。虽然数字信号的传输为了防止误码而会进行信道编码，增加传输码的冗余，例如增加监督位等来克服信号在信道传输过程中的错误，但这种检错纠错能力是有限的。例如当出现突发错误，出现大片误码时，这时信道的纠错是无能为力的。而卷积交织器可以将原来的信息码打乱，这时尽管出现大面积突发性错误，这些可以通过解交织器来进行分散，从而将大面积的错误较为平均地分散到不同的码段，利于信道纠错的实现。
In the digital transmission system, because of the existence of noise, channel fading and other interference factors, the transmission signal will be wrong, resulting in error code. Although channel coding and redundancy of transmission codes are increased in order to prevent errors in digital signal transmission, such as increasing supervisory bits, to overcome errors in channel transmission, this error detection and correction capability is limited. For example, when a burst error occurs and a large number of errors occur, the channel error correction is powerless. Convolutional interleaver can scramble the original information code. In spite of large-scale burst errors, these can be dispersed by de-interleaver, so that large-scale errors can be more evenly distributed to different code segments, which is conducive to the realization of channel error correction. (2019-05-14, Verilog, 367KB, 下载4次)
锁相环例程，锁相环测试相关，输出四个不同频率的波形
Phase-locked loop routine (2018-05-11, Verilog, 6029KB, 下载2次)
基于verilog编写的MSK调制程序，modsim仿真波形正确
Verilog based MSK modulation program written, modsim simulation waveform correct (2018-04-26, Verilog, 1059KB, 下载26次)
本文件用于测波形频率的verilog代码，是典型的数字频率计的源代码
This document is used to measure the frequency of the Verilog code, the source code of a typical digital frequency meter (2018-04-09, Verilog, 11KB, 下载4次)
波形数据上升下降沿的检测程序，已经经过仿真验证
The detection program of the rising descending edge of the waveform data has been verified by simulation (2018-03-01, Verilog, 36KB, 下载1次)
在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。
In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared. (2018-02-09, Verilog, 47016KB, 下载18次)
关于vga接口的程序 仿真成功 可供学习使用
VGA interface on the program, simulation success, for learning to use (2017-08-28, Verilog, 5810KB, 下载1次)
SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形
SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform (2017-08-02, Verilog, 4579KB, 下载5次)
多周期CPU的verilog代码，用vivado可以仿真出波形
multi-cycle CPU by verilog and using vivado to simulate. (2017-07-12, Verilog, 5738KB, 下载1次)
能够实现正弦波的输出以及通过频率控制字与相位控制字控制正弦波的相位与频率。
The output of the sine wave can be realized and the phase and frequency of the sine wave can be controlled by two control words. (2017-07-05, Verilog, 3KB, 下载2次)