MIPS处理器管道
MIPS Processor Pipeline (2023-12-07, Verilog, 0KB, 下载0次)
MIPS流水线处理器，，
MIPS Pipelined Processor,, (2023-10-20, Verilog, 0KB, 下载0次)
流水线MIPS处理器，，
Pipelined MIPS Processor,, (2023-09-28, Verilog, 0KB, 下载0次)
单周期32 MIPS处理器，
A single cycle 32 MIPS Processor, (2023-08-05, Verilog, 0KB, 下载0次)
超标量流水线MIPS处理器，
Superscalar Pipelined MIPS Processor, (2019-01-28, Verilog, 0KB, 下载0次)
具有管道的MIPS处理器。，
MIPS Processor with pipelines., (2019-07-26, Verilog, 0KB, 下载0次)
MIPS-R3000-模拟器-单循环-验证-，，
MIPS-R3000-simulator-singlecycle-verilog-,, (2016-06-29, Verilog, 0KB, 下载0次)
超标量管道处理器，用于处理MIPS指令。利用分支预测器和基本缓存内存。，
Superscalar pipeline processor designed to handle MIPS instructions. Utilizes branch predictor and basic cache memory., (2017-06-11, Verilog, 0KB, 下载0次)
单周期 MIPS 处理器仿真,
Single cycle MIPS processor simulation, (2018-12-07, Verilog, 0KB, 下载0次)
单周期管道MIPS处理器，
Single Cycle Pipeline MIPS Processor, (2020-02-12, Verilog, 0KB, 下载0次)
Brimstone：单周期MIP处理器，
Brimstone: Single Cycle MIPs Processor, (2020-05-13, Verilog, 0KB, 下载0次)
单时钟周期MIPS处理器，
Single Clock Cycle MIPS Processor, (2019-06-16, Verilog, 0KB, 下载0次)
OoOPs-无序MIPS（TM）处理器，
OoOPs - Out-of-Order MIPS (TM) Processor, (2014-07-17, Verilog, 0KB, 下载0次)
教育16位MIPS处理器，
Educational 16-bit MIPS Processor, (2019-02-16, Verilog, 0KB, 下载0次)
分别显示个位和十位的十二进制加法计数器verilog HDL设计
Design of Verilog HDL for 12 digit adder (2020-11-23, Verilog, 7893KB, 下载0次)
利用Verilog实现的简易SRAM控制器，内含源代码及仿真文件
A simple SRAM controller based on Verilog contains source code and simulation files (2020-11-10, Verilog, 344KB, 下载1次)
用verilog编写的OV5640摄像头DVP接口寄存器驱动程序，经过调试的，可以直接拷贝。已在Xilinx Spartan6 FPGA调试验证。
The OV5640 camera DVP interface register driver written in verilog can be copied directly after debugging. Tested and verified on Xilinx Spartan6 FPGA. (2020-03-16, Verilog, 4KB, 下载2次)
5接口下降沿D触发器实现，可直接使用于需要的场合
5 interface falling edge D trigger implementation (2019-11-30, Verilog, 446KB, 下载0次)
这是一个字节（8位）比较器，比较两个字节的大小，如a[7:0]大于b[7:0],则输出高电平，否则输出低电平。文件中包含测试程序。
This is a byte (8-bit) comparator, comparing the size of two bytes, such as a [7:0] greater than B [7:0], then output high level, otherwise output low level. The file contains test procedures. (2018-09-02, Verilog, 25KB, 下载1次)
这是一个改进的简单卷积器。此采用3片A/D转换器同时工作，并将采样过程计算、写入RAM的控制改为并行工作。此卷积器的采样频率为2.22MHz。
This is an improved simple convolution. This system uses three A / D converters to work at the same time, and changes the control of sampling process calculation and writing RAM to parallel operation. The sampling frequency of this convolution device is 2.22MHz. (2018-09-02, Verilog, 1KB, 下载0次)