红外接收机、发射机和遥控器的编码器和解码器模块，
Encoder and decoder modules for infrared receivers, transmitters and remotes, (2023-08-03, Verilog, 0KB, 下载0次)
8选1多路选择器,计数器的设计,三人表决器实验
8 choose 1 Multiplexer, counter design, three voting experiment (2021-03-01, Verilog, 2084KB, 下载0次)
数字滤波器设计 fpga相关知识 程序示例资料
DIGITAL FILTER FPGA design knowledge, sample program information (2021-02-27, Verilog, 23198KB, 下载0次)
使用Verilog编写的计数器，能够实现计数功能
Counter,counting function (2020-11-25, Verilog, 69KB, 下载0次)
计数器是由基本的计数单元和一些控制门所组成，计数单元则由一系列具有存储信息功能的各类触发器构成，这些触发器有RS触发器、T触发器、D触发器及JK触发器等。
本代码在fpga中实现累加器的功能
The counter is composed of a basic counting unit and some control gates, while the counting unit is composed of a series of triggers with the function of storing information. These triggers include RS trigger, t trigger, D trigger and JK Trigger.
This code realizes the function of accumulator in FPGA (2020-09-16, Verilog, 1412KB, 下载0次)
闹钟系统各模块代码，分频器，计时器，键盘，数码管，寄存器，和总的代码。
Alarm system module code (2020-05-18, Verilog, 17KB, 下载0次)
用Verilog HDL语言写的模60计数器，可以自己随意修改模值，改为任意模值计数器
Module 60 counter.You can modify the module value at random and change it to any modulus counter. (2020-05-17, Verilog, 1KB, 下载0次)
4位二进制除法器，通过FPGA控制TLC1196AD转换器实现除法器，采用了移位相减法。
4-bit binary divider (2019-11-21, Verilog, 810KB, 下载0次)
verilog语言半加器全加器好好看看吧希望对大家有用
Verilog language, half adder, full adder. Have a look. I hope it will be useful to you. (2019-10-28, Verilog, 24KB, 下载0次)
半加器实现，简单的半加器，作为新手实验用
Semi-adder implementation, simple semi-adder, as a novice experiment (2019-06-12, Verilog, 2960KB, 下载6次)
用VIVADO实现最简单的分频器，分成了三个频率
Using VIVADO to realize the simplest frequency divider, which is divided into three frequencies (2019-04-17, Verilog, 473KB, 下载1次)
SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器
SRAM 8K*8
Chip memory
Chip memory (2018-08-26, Verilog, 3KB, 下载14次)
基于D触发器时序电路，实现特定输入2进制序列的检测
Detection of specific input 2 binary sequence based on D flip flop sequential circuit (2018-07-12, Verilog, 1KB, 下载0次)
移位寄存器模块用于存储串行输入滤波器的数据；乘加计算模块用于fir计算
The shift register module is used to store data of serial input filter, and the multiplier calculation module is used for FIR calculation. (2018-06-30, Verilog, 1KB, 下载3次)
fpga，蜂鸣器，控制，程序，quartus ii
FPGA, buzzer, control, program, Quartus II (2018-05-23, Verilog, 720KB, 下载0次)
几个Verilog例程，包含寄存器、锁存器、触发器等。
Several Verilog routines include registers, latches, triggers, and so on. (2018-05-11, Verilog, 2812KB, 下载0次)
CAN 2.0协议控制器，非常全面的控制器Verilog代码，可靠通信，可放心使用。
CAN Bus 2.0 Controller. (2018-01-19, Verilog, 33KB, 下载24次)
用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。
Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide. (2017-12-22, Verilog, 1KB, 下载11次)
3阶cic滤波器，16位输出，32倍降采样处理
The 3 order CIC filter, 16 bit output, 32 fold down sampling processing (2017-11-07, Verilog, 1KB, 下载10次)
10秒计数器模块ＶＨＤＬ源程序，在FPGA中实现计数器功能
10 seconds counter module VHDL source code, in FPGA realize counter function (2017-07-09, Verilog, 1284KB, 下载2次)