计算器Verilog
Calculator Verilog (2024-04-22, Verilog, 0KB, 下载0次)
基于FPGA的高性能JPEG编解码器加速器
High-performance FPGA-based JPEG codec accelerator (2018-12-01, Verilog, 2317KB, 下载1次)
Verilog中的流水线VGA文本字符生成器控制器
Pipelined VGA text character generator controller in Verilog (2018-12-08, Verilog, 944KB, 下载0次)
用于FPGA的Verilog 2001中实现的SPI总线从机和触发器寄存器存储器映射
SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs (2019-12-15, Verilog, 26KB, 下载0次)
Verilog中的Sega Genesis Mega Drive控制器编码器
Sega Genesis Mega Drive controller encoder in Verilog (2019-05-15, Verilog, 77KB, 下载0次)
基于系统Verilog的DDR3SDRAM存储器控制器设计与综合
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog (2018-11-06, Verilog, 32594KB, 下载0次)
verilog语言实现锁存器，可在quartusII运行
It can run in Verilog II (2021-03-16, Verilog, 1KB, 下载0次)
D触发器的实现，里面有teshbench文件及源文件
Implementation of D flip flop (2020-11-22, Verilog, 32KB, 下载0次)
定时器，可以完成倒计时，分别由时分秒的倒计时，可以在随意时间按下按键停止计时。
Timer, can complete the countdown, respectively by the minute of the countdown, you can press the button at any time to stop timing. (2020-03-06, Verilog, 14KB, 下载0次)
SPI控制器MASTER,可支持多路片选
spi master Controller (2019-12-27, Verilog, 1KB, 下载2次)
xilinx SP6系列的3-8译码器实现
Implementation of Xilinx SP6 Series 3-8 Decoder (2019-07-22, Verilog, 148KB, 下载1次)
一个简单的轮换优先级仲裁器，共四个master
Rotation Priority Arbitrator (2019-01-23, Verilog, 1KB, 下载3次)
温度传感器DS18B20解析代码，已验证
Temperature sensor DS18B20 parse code, has been verified (2018-12-27, Verilog, 2KB, 下载0次)
内含基于FPGA实现，智力抢答器，分频器，和滤波器三种基础Verilog编写教程，有利于新手对FPGA练习
It contains three basic Verilog tutorials: implementation based on FPGA, intelligent answering device, frequency divider and filter, which are helpful for novices to practice on FPGA. (2018-12-25, Verilog, 4927KB, 下载2次)
利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench
Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language (2018-08-06, Verilog, 258KB, 下载3次)
关于FPGA的一些例程，包括CORDIC数字计算机的设计，RS(204,188)译码器的设计等。
Some routines on FPGA include the design of CORDIC digital computers, the design of RS (204188) decoders, etc. (2018-07-21, Verilog, 27KB, 下载8次)
CAN驱动器MCP2515驱动，verilog编写，实测可用
CAN driver MCP2515 driver, Verilog written, measured available (2018-07-04, Verilog, 9KB, 下载48次)
通过连续调用半加器组成一位全加器，再次调用一位全加器组成4位全加器。对初学者有一定的指导作用。
Through the continuous call half adder of a full adder, called again of a full adder four full adder. For beginners have a certain guiding role. (2018-05-28, Verilog, 1975KB, 下载0次)
SATA控制器代码，来自opencore
code for SATA controller, from opencore (2017-11-08, Verilog, 39KB, 下载21次)
三八译码器，四位加法器，EDA实验，用verilog编写
EDA experiment with verilog language (2017-10-30, Verilog, 1KB, 下载3次)