RISC-V处理器所有子模块的RTL Verilog文件（例如，寄存器文件、指令存储器等）。然后，实现RISC-V处理器的顶层模块
the RTL Verilog files for all submodules of the RISC-V processor (e.g. Register File, Instruction Memory, etc.). Then, implementing the top module of the RISC-V processor (2024-02-26, Verilog, 0KB, 下载0次)
FPGA扬声器
FPGA Speaks (2023-10-31, Verilog, 0KB, 下载0次)
8b10b编码器和解码器（verilog）+测试台（systemverilog.）的源代码，
source code of the 8b10b encoder and decoder (verilog) + testbench (systemverilog), (2022-05-19, Verilog, 0KB, 下载1次)
音频和红外遥控pdm调制器和解调器的verilog实现，
verilog implement of pdm modulator and demodulator for audio and infrared remote, (2023-08-12, Verilog, 0KB, 下载0次)
在FPGA上实现梳妆滤波器的方案，包含滤波器原理实现方案，以及仿真图
The scheme for implementing a makeup filter on FPGA, including the filter principle implementation scheme and simulation diagram (2023-07-19, Verilog, 313KB, 下载2次)
基于FPGA的I2C到RS-232串行转换器总线监视器
FPGA-based I2C to RS-232 serial converter bus monitor (2016-01-29, Verilog, 243KB, 下载0次)
ConvNN_FPGA_加速器，，
ConvNN_FPGA_Accelerator,, (2015-12-17, Verilog, 13646KB, 下载0次)
带有集成RS232调试器的Verilog I2C初始化器。
A Verilog I2C initializer with integrated RS232 debugger. (2022-08-19, Verilog, 27KB, 下载0次)
JPEG编码器Verilog
JPEG Encoder Verilog (2022-10-31, Verilog, 209KB, 下载1次)
一个4位宽的十进制计数器，用verilog语言实现
A 4-bit wide decimal counter, using Verilog language (2021-04-24, Verilog, 29KB, 下载0次)
用modelsim实现2选1数据选择器的功能
Implementation of 2-out-of-1 data selector (2021-04-21, Verilog, 123KB, 下载0次)
高速流水的SDRAM控制器，最高速度可达速度在200M左右
high speed SDRAM controller (2019-06-17, Verilog, 14562KB, 下载3次)
VHDL编写的，利用蜂鸣器实现播放乐曲的功能
using VHDL and making buzzle work (2019-06-09, Verilog, 3369KB, 下载2次)
基础decoder，encoder，mux，priority encoder 代码以及testbench
basic decoder, encoder, mux, priority encoder code and testbench (2019-05-15, Verilog, 3378KB, 下载0次)
1. 利用一位半加器设计八位全加器
2. 进行功能仿真
1. Design of an eight-bit full adder by using a one-and-a-half adder
2. Functional simulation (2019-03-22, Verilog, 678KB, 下载0次)
36阶fir低通滤波器
附带仿真文件‘
可直接运行’
36 order FIR low pass filter
Incidental simulation file '
Can run directly ' (2018-06-12, Verilog, 7543KB, 下载11次)
SDRAM控制器，可控制SDRAM进行读写存储，含SDRAM控制器源码及SDRAM说明文档
SDRAM Controller have source code and spec (2018-05-09, Verilog, 758KB, 下载11次)
用verilog语言编写一个计数器，改参数实现不同时间的计数器
Writing a counter in the Verilog language (2018-02-28, Verilog, 381KB, 下载1次)
本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。
The main function of this code is PPM decoding. (2017-11-27, Verilog, 168KB, 下载18次)
介绍了fpga开发的的数个工程源码，包括按键，时钟，AD/DA，VGA，数字示波器等
Introduced FPGA development of several engineering source code, including buttons, clock, AD/DA, VGA, digital oscilloscope, etc. (2017-08-23, Verilog, 90088KB, 下载11次)