Altera DE2-115板中测试微处理器回购的设置
setup for testing microprocessor repo in Altera DE2-115 board (2024-04-05, VHDL, 0KB, 下载0次)
用于低延迟云集成的卷积神经网络加速器（VGG16）。，
Convolutional neural network accelerator (VGG16) for low-latency cloud integration., (2021-07-08, VHDL, 0KB, 下载0次)
八选三数据选择器，实八选一功能，包含输入输出使能端
Three out of eight data selector (2021-04-11, VHDL, 3035KB, 下载0次)
quartus的破解软件，里面有说明文档
Quartus crack software, which contains documentation. (2020-12-27, VHDL, 105KB, 下载12次)
实现16bit的移位功能 ，使用Verilog语言实现，简单易懂
Realize the shift function of 16bit, using Verilog language, easy to understand (2019-01-21, VHDL, 25KB, 下载0次)
存储器的verilog实现，在linux下使用gvim编写
the memory implement based on verilog (2018-11-27, VHDL, 84KB, 下载0次)
基于VHDL的计时器，是由自己写的程序，亲测可用
VHDL based timer, is written by oneself, pro test available. (2018-08-26, VHDL, 865KB, 下载0次)
用VERILOG设计完成一个4位行波进位的加减法运算器，要求有溢出和进位标志，并封装成模块。
A 4 bit traveling wave carry and add and subtract arithmetic unit is designed and implemented by VERILOG. It requires overflow and carry marks and is encapsulated into modules. (2018-06-15, VHDL, 317KB, 下载0次)
4对2编码器实现 输入0001 0010 0100 1000时输出00 01 10 11
INPUT:I3,I2,I1,I0;OUTPUT:A,B
when I3,I2,I1,I0=0,0,0,1 A,B=0,0
0,0,1,0 0,1
0,1,0,0 1,0
1,0,0,0 1,1 (2018-05-12, VHDL, 4018KB, 下载0次)
VHDL实验中，实现分频与数码管显示。掌握BCD-七段显示译码器的功能和设计方法；
掌握用硬件描述语言的方法设计组合逻辑电路——BCD-七段显示译码器。
In the VHDL experiment, frequency division and digital tube display are realized. (2018-04-17, VHDL, 20732KB, 下载2次)
verilog四则运算，包括加法器、乘法器、除法器，不过都是拾人牙慧，整理一下，供新手参考。
Verilog four operations, including the adder, multiplier and divider, but are written, tidy, for novice reference. (2017-12-01, VHDL, 4KB, 下载6次)
带有异步清零、异步置位功能的边沿JK触发器
With asynchronous reset, asynchronous setting function of edge JK flip-flop (2016-04-06, VHDL, 10KB, 下载3次)
sdram控制器data_path命令接口模块的VHDL源程序文件，可直接用
sdram data_path (2010-03-20, VHDL, 1KB, 下载4次)
实现窗口搜索算法的并行系统——顶层控制器
Search algorithm to achieve the window parallel systems- the top-level controller (2009-12-25, VHDL, 3KB, 下载2次)
实现窗口搜索算法的并行系统——协同处理器
Search algorithm to achieve the window parallel systems- co-processor (2009-12-25, VHDL, 3KB, 下载1次)
一位加法全加器，可以实现低位进位输入和高位进位输出。
full adder (2009-12-24, VHDL, 77KB, 下载6次)
一个简单的由vhdl代码描述的分频器模型
it is code writing by vhdl,and it is used for divede clk (2009-11-24, VHDL, 235KB, 下载3次)
FIFO RAM 存储器以FIFO形式进行的读取
FIFO RAM (2009-07-24, VHDL, 324KB, 下载9次)
本分频器不仅可以达到任意的整数分频，还可以达到半分频，例如3.5分频
The divider can be achieved not only arbitrary integer frequency, but also semi-sub-band can be achieved, for example, frequency of 3.5 points (2009-07-04, VHDL, 267KB, 下载4次)
该程序包为FPGA的例子，用FPGA来设计MP3播放器
The package for the FPGA example, using FPGA to design MP3 player (2008-12-23, VHDL, 165KB, 下载96次)