在本项目中，您需要实现基于哈佛体系结构的32位单周期微体系结构MIPS处理器。...，
In this project, you are required to implement a 32-bit single-cycle microarchitecture MIPS processor based on Harvard Architecture. The single-cycle microarchitecture executes an entire instruction in one cycle. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle. (2023-09-18, Verilog, 0KB, 下载0次)
在这个项目中，我们将为RISC-V处理器实现一个简单的缓存系统。为了简单起见，我们将集成cac...，
In this project, we will work on implementing a simple caching system for the RISC-V processor. For simplicity, we will integrate the caching system with the single-cycle implementation. (2023-09-03, Verilog, 0KB, 下载0次)
FPGA Cyclone IV开发板系统，由RISC-V CPU、定制操作系统、DMA、外围设备的控制器和驱动程序组成。，
System for FPGA Cyclone IV dev board that consist of RISC-V CPU, custom OS, DMA, controllers and drivers for peripherals., (2023-09-01, Verilog, 0KB, 下载0次)
毕业设计：在FPGA工具包上实现基于哈佛体系结构的32位多周期微体系结构RISC V处理器（sparta...，
Graduation Project : Implement a 32-bit multi-Cycle microarchitecture RISC V processor based on Harvard Architecture on a FPGA kit(spartan-6) using Xilinx’s tool “ISE14.7”. (2023-08-21, Verilog, 0KB, 下载0次)
VeriRISC模型是一种用Verilog HDL编码的非常精简的指令集处理器。其指令由三位运算组成...，
The VeriRISC model is a very-reduced-instruction-set processor coded in the Verilog HDL. Its instruction consists of a three-bit operation code and a five-bit operand. That restricts its instruction set to eight instructions and its address space to 32 locations (2023-07-18, Verilog, 0KB, 下载0次)
在这个项目中，我实现了一个基于Harvard Architect的32位单周期微体系结构MIPS处理器。在ot中...
In this project, I implement a 32-bit single-cycle microarchitecture MIPS processor based on Harvard Architect. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle. I write the RTL Verilog files for all sub-modules of the MIPS processor (e.g. Register File, (2022-09-01, Verilog, 13KB, 下载0次)
RECON项目为Nios II微控制器系统和工具链创建库。图书馆包括一个收藏品...
The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs. (2018-12-31, Verilog, 1235KB, 下载0次)
5级Pipelend Risc-v处理器，包含危险检测单元和前置单元，并支持R-Typr、I-type、S-typ...
5-stage piplened Risc-v processor that contains hazard detection unit and foward unit and support R-Typr,I-type,S-type and conditional branch instructions (2023-03-28, Verilog, 10KB, 下载0次)
由4人小组设计的流水线RISC-V处理器的Verilog HDL代码和文档，是一个小型项目。包括...
Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework. (2023-06-19, Verilog, 4580KB, 下载0次)
在一个3人的团队中工作，在System Verilog中从头开始完成流水线RISC-V处理器，包括双L1...
Worked on a team of 3 to complete a pipelined RISC-V processor from scratch in System Verilog, complete with dual L1 Caches, a L2 cache, prefetching, and a branch predictor. (2020-11-11, Verilog, 1182KB, 下载0次)
RISC-V 32位处理器，运行2.5D迷宫游戏；为2018年冬季瓦拉瓦拉大学CPTR380建造
RISC-V 32-bit processor that runs a 2.5D maze game; Built for CPTR380 Winter of 2018 at Walla Walla University (2018-11-28, Verilog, 158KB, 下载0次)
LCAI-TIHU硬件是一种人工智能推理处理器，由RISC-V cpu、nvdla、NoC总线、PCIe模块、DDR、SRAM、b...
LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals. (2023-01-06, Verilog, 50641KB, 下载0次)
VSDBabySoC是一种小型混合信号SoC，包括PLL、DAC和名为RVMYTH的基于RISCV的处理器。
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH. (2022-01-04, Verilog, 10554KB, 下载0次)
这个IP核是一个小型的，简单的SDRAM控制器，用于为16位SDRAM芯片提供32位流水线的二叉树接口。
当访问开放行时，读写可以流水线实现完整的SDRAM总线利用率，但是读写之间的切换需要几个周期。
This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip.
When accessing open rows, reads and writes can be pipelined to achieve full SDRAM bus utilization, however switching between reads & writes takes a few cycles.
The row management strategy is to leave active rows open until a row needs to be closed for a periodic auto refresh or until that bank needs to open another row due to a read or write request.
This IP supports supports 4 open active rows (one per bank). (2017-08-15, Verilog, 24KB, 下载2次)